ICCD 2019


    Important Dates:

    Abstract Submission
    21-June-2019, 11:59pm AOE
    28-June-2019, 11:59pm AOE(Extended)

    Paper Submission
    28-June-2019, 11:59pm AOE
    7-July-2019, 11:59pm AOE(Extended)

    Notification
    9-Sept-2019

    Camera-Ready
    30-Sept-2019

    Contact Us

    Web Chair

2019 IEEE International Conference on Computer Design (ICCD)


ICCD 2019: Tutorial Sessions

Note: The tutorials are open to all registered conference attendees at no additional cost.

Tutorial 1: RRAM Technology for Efficient In-Memory Computing Architecture

Organizer:

  • Baker Mohammad, Heba Abunahla and Yasmin Halawani, Khalifa Universitym U.A.E

Abstract

In-memory computing (IMC) approach is gaining an increased attention as a potential candidate to overcome the challenges and limitations associated with traditional computing (von Neumann) on device and architectural levels. IMC is bio-inspired approach that combines both storage and computation processes within the same physical element. Resistive-RAM (RRAM) technology, especially Memristor, exhibits many interesting characteristics such as its non-volatility nature, analog behavior, nano-scale size, relatively fast read and write operations, high resistance ratio and potential compatibility with CMOS technology. Such features make it suitable for IMC architectures and applications. Furthermore, the continuous response of Memristor state variable to an applied input voltage makes it an ideal candidate to perform multiply and accumulate (MAC) operations efficiently. Many digital signal processing algorithms are computationally-intensive and rely heavily on the MAC operations. Moreover, memristor fingerprint I-V characteristic may alter against specific environmental changes, which generates the interest toward device deployment in sensing applications. In addition, Memristor’s non-linear, analog behavior can be exploited for security applications. Despite all the aforementioned promising characteristics, Memristor device technology is still immature and experiences many challenges in the design and automation side hindering it from commercialization at this stage. This tutorial introduces Memristor technology at the device physics level. It also presents the different models that captures the Memristor switching behavior, and the design space where noise-margin can be relaxed for lower write energy and shorter switching times. Also, the tutorial highlights the challenges associated with the crossbar architecture and some possible solutions to overcome them. The seminar will end with mainstream applications for Memristor IMC paradigm investigated by KU team and show good results.

Outline:
14.00-14.40: Introduction to the tutorial
• Motivation and overview of limitation of current architecture and technology
1. Existing option (GPU, TPU, etc.)
2. Need for new technology and new architecture
14.40-15.40: RRAM
• Introduction to RRAM focusing on Memristor (MR) device and types of MR uni-polar, bi-polar
• Switching mechanism: fuse-anti-fuse, valence change memory, electrochemical metallization memory
• Electrical characterization of each type
• Device modeling including matlab and spice models
16.00-16.50: MR design Space and challenges
• Designing with MR, Accuracy, noise margin, retention time. MR crossbar challenges: sneak path, state drift, conductance tunning
17.00-18.00: MR application Examples: Computing, Security & Sensors
• Image Compression, Search Engine, CNN, Security Application, Sensor application

Tutorial 2: Estimation Tools for Wireless On-Chip Networks with an Application to Approximated Deep Neural Network Inference

Organizer:

  • Davide Patti, University of Catania, Italy

Abstract

As the number of cores integrated into the same chip increases, the role played by the on-chip communication system becomes more and more important. To face with the above problem, current manycore architectures use a Network-on-Chip (NoC) as communication backbone. After introducing the main concepts of NoC architectures, this tutorial will give attendees the opportunity of start playing, with the help the same co-author of the platform, with the well-known Noxim simulation tool to assess, in a cycle-accurate manner, the performance and power figures of NoC and Wireless NoC (WiNoC) architectures and to understand what takes place behind the scenes. In addition, will be also introduced some tools that authors of Noxim are currently developing for the high-level estimation of approximated computing techniques applied to NoC-based inference in convolutional neural networks (CNN).

Outline:
14.00-15.00: Introduction to Network on Chip main topics
15.00-16.00: Installation and Usage of Noxim
16.00-17.00: Noxim internals: Advanced Usage
17.00-18.00: NoC for Deep Neural Networks: estimation with NoCNN tool

Attendees interested in testing the demos shown during the tutorial can bring their own laptops with a GNU/Linux OS (preferably Ubuntu) already installed.

Tutorial Chairs:

For any questions on submission, please contact the Tutorial Session Chairs (Christian Pilato and Sara Vinco).