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MONDAY |
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| 8:00-9:00 |
Registration and
opening |
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| 9:00-10:00 |
Keynote 1: Designing
"Artificial Brains" for Next-Generation Autonomous Systems (Luca
Benini, ETHZ & Università di Bologna) |
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| 10:00-11:05 |
Session 1A:
Logic and Circuit Design |
Session
1B: In-Memory Systems and Memory Architectures |
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| 11:05-11:30 |
Coffee break |
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| 11:30-12:45 |
Session 2A:
Energy Efficient HW Architectures |
Session
2B: Security |
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| 12:45-14:15 |
Lunch break |
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| 14:15-15:45 |
Session
3A: ML-supported HLS and Design |
Tutorial
1: Expedited development of novel RISC-V instructions through an
emulation-simulation framework |
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| 15:45-16:15 |
Coffee break |
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| 16:15-17:30 |
Session 4A:
Computing Systems for Learning, and Learning for Computing Systems |
Session
4B: Persistent Memories |
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| 18:00-19:30 |
Welcome Reception |
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MONDAY - SESSIONS
DETAILS |
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| LCD1 |
Session 1A: Logic and Circuit Design (chair: Lilas Alrahis) |
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| R |
ChaoSen: Security
Enhancement of Image Sensor through in-Sensor Chaotic Computing (Nedasadat
Taheri, Sepehr Tabrizchi, Shaahin Angizi and Arman Roohi) |
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| R |
Memristive
Logic-in-Memory Implementation with Area Efficiency and Parallelism (Ikkyum
Kim and Heechun Park) |
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| R |
S3M: Static
Semi-Segmented Multipliers for Energy-efficient DNN Inference Accelerators
(Mingtao Zhang, Quan Cheng, Hiromitsu Awano, Longyang Lin and Masanori
Hashimoto) |
| S |
Optimizing Quantum
Circuit Synthesis with Dominator Analysis (Giacomo Lancellotti, Giovanni
Agosta, Alessandro Barenghi and Gerardo Pelosi) |
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| HW2 |
Session 1B: In-Memory Systems and Memory Architectures (chair: Hu He) |
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| R |
MemSort: In-Memory
Sorting Architecture (Rui Liu, Xiaoyu Zhang, Xinyu Wang, Feng Min, Zhejian
Luo, Xiaoming Chen, Yinhe Han and Minghua Tang) |
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| R |
MuSA: Multi-Sketch
Accelerator with Hybrid Parallelism and Coalesced Memory Organization (Sunan
Zou, Bizhao Shi, Ziyun Zhang and Guojie Luo) |
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| R |
CoPIM: A Collaborative
Scheduling Framework for Commodity Processing-in-memory Systems (Shunchen
Shi, Xueqi Li, Zhaowu Pan, Peiheng Zhang and Ninghui Sun) |
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| R |
ChameSC: Virtualizing
Superscalar Core of a SIMD Architecture for Vector Memory Acces (Zhongzhu Pu,
Guangda Zhang, Tiejian Zhang, Chen Zhang, Youhui Zhang and Xia Zhao) |
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| HW4 |
Session 2A: Energy Efficient HW Architectures (chair: Sungju Ryu) |
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| R |
Multi: Reduce Energy
Overhead of Criticality-aware Dynamic Instruction Scheduling for Energy-efficient Performance (Honglan Zhan,
Chenxi Wang, Xin Wang, Chun Yang, Xianhua Liu and Xu Cheng) |
| R |
T-BUS: Taming Bipartite
Unstructured Sparsity for Energy-Efficient DNN Acceleration (Ning Yang,
Fangxin Liu, Zongwu Wang, Zhiyan Song, Tao Yang and Li Jiang) |
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| R |
PS4: A Low Power SNN
Accelerator with Spike Speculative Scheme (Wang Zongwu, Fangxin Liu, Xin Tang
and Li Jiang) |
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| R |
PCCL: Energy-efficient
LLM Training with Power-aware Collective Communication (Ziyang Jia, Daniel
Wong and Laxmi Bhuyan) |
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| S |
Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage (Yamilka Toca-Díaz, Ruben
Gran Tejero and Alejandro Valero) |
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| TVS1 |
Session 2B: Security (chair: Arman Roohi) |
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| R |
A Semi Black-Box
Adversarial Bit-Flip Attack with Limited DNN Model Information (Behnam
Ghavami, Mohammad Shahidzadeh, Man Sadati, Lesley Shannon and Steve Wilton) |
| R |
BlinK: Breaking Parallel
Implementation of CRYSTALS-Kyber with Side-Channel Attack (Jian Wang,
Weiqiong Cao, Hua Chen and Haoyuan Li) |
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| R |
Hound: Locating
Cryptographic Primitives in Desynchronized Side-Channel Traces Using
Deep-Learning (Davide Galli, Giuseppe Chiari and Davide Zoni) |
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| R |
Interpretable Risk-aware
Access Control for Spark: Blocking Attack Purpose Behind Actions (Wenbo Wang,
Tao Xue, Shuailou Li, Zhaoyang Wang, Boyang Zhang and Yu Wen) |
| S |
TDM: Time and Distance
based Metric for Quantifying Information Leakage Vulnerabilities in SoCs
(Avinash Ayalasomayajula, Henian Li, Hasan Al-Shaikh, Sujan Kumar Saha and
Farimah Farahmandi) |
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| EDA2 |
Session 3A: ML-supported HLS and Design (chair: Cristina Silvano) |
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| R |
Transformer-Characterized
Approach for Chip Floorplanning: Leveraging HyperGCN and DTQN (Wenbo Guan,
Xiaoyan Tang, Hongliang Lu, Jingru Tan, Jinlong Wang and Yuming Zhang) |
| R |
Elastic EDA: Auto-scaling
Cloud Resources for EDA Tasks via Learning-based Approaches (Linyu Zhu,
Xingyu Ma, Shaogang Hao, Yushan Pan and Xinfei Guo) |
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| R |
RNC: Efficient RRAM-aware
NAS and Compilation for DNNs on Resource-Constrained Edge Devices (Kam Chi
Loong, Shihao Han, Sishuo Liu, Ning Lin and Zhongrui Wang) |
| R |
AutoVCoder: A Systematic
Framework for Automated Verilog Code Generation using LLMs (Mingzhe Gao,
Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li and Minyi
Guo) |
| R |
Reinforcement
Learning-driven Co-scheduling and Diverse Resource Assignments on NUMA
Systems (Urvij Saroliya, Eishi Arima, Dai Liu and Martin Schulz) |
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| S |
Rethinking High-Level
Synthesis Design Space Exploration from a Contrastive Perspective (Huiliang
Hong, Chenglong Xiao and Shanshan Wang) |
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| T1 |
Tutorial 1: Expedited
development of novel RISC-V instructions through an emulation-simulation
framework |
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Julian Pavon, Ivan Vargas
Valdivieso, Carlos Rojas Morales, Nishil Talati and Adrian Cristal |
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| CS4 |
Session 4A: Computing
Systems for Learning, and Learning for Computing Systems (chair: Di Liu) |
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| R |
ParaCkpt: Heterogeneous
Multi-path Checkpointing Mechanism for Training Deep Learning Models
(Shucheng Wang, Qiang Cao, Kaiye Zhou, Jun Xu, Zhandong Guo and Jiannan Guo) |
| R |
RTDeepEnsemble: Real-time
DNN Ensemble Method for Machine Perception Systems (Zitong Bo, Chaoping Guo,
Ying Qiao, Chang Leng and Hongan Wang) |
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| R |
Interference-Aware DNN
Serving on Heterogeneous Processors in Edge Systems (Yeonjae Kim, Igjae Kim,
Kwanghoon Choi, Jeongseob Ahn, Jongse Park and Jaehyuk Huh) |
| R |
HOLES: Boosting Large Language Models Efficiency with
Hardware-friendly Lossless Encoding (Fangxin Liu, Ning Yang, Zhiyan Song,
Zongwu Wang and Li Jiang) |
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| S |
OLSATM: Online Learning
based State-Aware Task Migration on S-NUCA Many-cores (Yandong He, Guangda
Zhang, Yongjun Zhang, Hengzhu Liu and Renzhi Chen) |
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| S |
Co-Designing a 3D Transformation Accelerator for Versal-Based Image Registration (Paolo Salvatore Galfano, Giuseppe Sorrentino, Eleonora D'Arnese and Davide Conficconi) |
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| CS6 |
Session 4B: Persistent Memories (chair: Jinhua Cui) |
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| R |
Read-Optimized Persistent
Hash Index for Query Acceleration through Fingerprint Filtering and Lock-Free
Prefetching (Renzhi Xiao, Dan Feng, Yuchong Hu, Hong Jiang, Lin Wang, Yucheng
Zhang, Lanlan Cui, Guanglei Xu and Fang Wang) |
| R |
Optimizing Structural
Modification Operation for B+Tree on Byte-Addressable Devices (Dingze Hong,
Jinlei Hu, Jianxi Chen, Dan Feng and Jian Liu) |
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| R |
FastMatch: Enhancing Data
Pipeline Efficiency for Accelerated Distributed Training (Jianchang Su,
Masoud Rahimi Jafari, Yifan Zhang and Wei Zhang) |
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| R |
Multi-Stage Dynamic Cuckoo Filters (Jun Su, Yinjin Fu and Nong
Xiao) |
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| S |
Persistent Spiral Storage (Wenyu Peng, Tao Xie and Paul
Siegel) |
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TUESDAY |
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| 9:00-10:00 |
Keynote 2: From VLSI
through Software: Optimizing the Computing Stack for Generative AI (Brucek
Khailany, NVIDIA) |
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| 10:00-11:10 |
Session 5A:
RISC-V Advancements |
Session
5B: SW Architectures for Learning |
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| 11:10-11:30 |
Coffee break |
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| 11:30-12:50 |
Session 6A: SSD
Design and Optimization |
Session
6B: Test and Verification |
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| 12:50-14:15 |
Lunch break |
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| 14:15-15:45 |
Session 7A:
Advancements in Hardware Architectures |
Tutorial
2: Adaptive CNN Execution on Edge FPGAs |
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| 15:45-16:15 |
Coffee break |
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| 16:15-17:35 |
Session 8A:
Memory-efficient Design |
Session
8B: SW Architectures for Optimization |
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| 19:30-22:00 |
Social Dinner |
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TUESDAY - SESSIONS
DETAILS |
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| HW1 |
Session 5A: RISC-V Advancements (chair: Francesco Ratto) |
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| R |
Advanced Dynamic
Scalarisation for RISC-V GPGPUs (Matthew Naylor, Alexandre Joannou, Theo
Markettos, Paul Metzger, Simon Moore and Timothy Jones) |
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| R |
Extending RISC-V for
Efficient Overflow Recovery in Mixed-Precision Computations (Luca Bertaccini,
Siyuan Shen, Torsten Hoefler and Luca Benini) |
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| R |
HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing from Embedded to High-Performance Systems
(Cyril Koenig, Bjorn Forsberg and Luca Benini) |
| S |
Ventus: A
High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension
(Jingzhou Li, Kexiang Yang, Chufeng Jin, Xudong Liu, Zexia Yang, Fangfei Yu,
Yujie Shi, Mingyuan Ma, Li Kong, Jing Zhou, Hualin Wu and Hu He) |
| S |
vCLIC: Towards Fast
Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems (Enrico
Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo
and Luca Benini) |
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| SW2 |
Session 5B: SW Architectures for Learning (chair: Nuno Roma) |
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| R |
PCC: An End-to-End
Compilation Framework for Neural Networks on Photonic-Electronic Accelerators
(Bohan Hu, Yinyi Liu, Zhenguo Liu, Wei Zhang and Jiang Xu) |
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| R |
Tango: Low Latency
Multi-DNN Inference on Heterogeneous Edge Platforms (Zain Taufique, Aman
Vyas, Antonio Miele, Pasi Liljeberg and Anil Kanduri) |
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| R |
Private Tensor Freezing
for an Efficient Federated Learning with Homomorphic Encryption (Valentino
Peluso, Erich Malan, Andrea Calimera and Enrico Macii) |
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| S |
Pseudo-Sim: An Accurate
Analytical Modeling Framework for Systolic Array Architectures (Dan Sturm and
Sajjad Moazeni) |
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| S |
Fine-Grained Shared Cache
Interference Analysis using Basic Block's Execution Time (Yixuan Zhu, Wenqi
Lou, Yinkang Gao, Binze Jiang, Xiaohang Gong and Xi Li) |
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| CS1 |
Session 6A: SSD Design and Optimization (chair: Masanori Hashimoto) |
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| R |
SchInFS: A File System
Integrating Functions of the Block IO Scheduler for ZNS SSDs (Jintong Zhang,
Haichuan Hu, Jianxi Chen and Yekang Zhan) |
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| R |
GCC: Optimizing Space
Efficiency and Read Latency of SSDs with Workload-Aware Garbage Collection
Aided Compression (Linhui Liu, Yunfei Gu, Chenhao Zhu, Chentao Wu, Jie Li and
Minyi Guo) |
| R |
LBZ: A Lightweight Block
Device for Supporting F2FS on ZNS SSD (Yongpeng Yang, Dejun Jiang, Bo Jiang,
Hao-Chiang Hsu, Liang Peng and Zifeng Yang) |
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| R |
RAID45: Hybrid
Parity-based RAID for Reducing Parity Write Wear on High-Density SSDs (Jialin
Liu, Yujiong Liang, Yunpeng Song and Liang Shi) |
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| S |
SmartNetSSD: Exploiting
Path Resources for Read Performance Improvement in Network-Based SSDs (Jinhua
Cui, Feiyu Chen, Lu Li, Shiqiang Nie and Laurence T. Yang) |
| S |
SuperMap: High-Performance and Flexible Memory-Mapped IO for Fast Storage Device (Wenqing Jia, Dejun Jiang and Jin Xiong) |
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| TVS2 |
Session 6B: Test and Verification (chair: Caaliph Andriamisaina) |
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| R |
Safe Speculation for
CHERI (Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Alexandre Joannou,
Jessica Clarke, John Baldwin, Brooks Davis, Peter G. Neumann, Robert N. M.
Watson and Simon W. Moore) |
| R |
APE-FV: Concolic Testing
for RTL Functional Verification Using Adpative Path Exploration (Ziyue Zheng,
Xiangchen Meng and Yangdi Lyu) |
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| R |
HAp-FT: A Hybrid
Approximate Fault Tolerance Framework for DNN Accelerator (Xiaohui Wei,
Chenyang Wang, Zeyu Guan, Fengyi Li and Hengshan Yue) |
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| R |
LLM-TG: Towards Automated
Test Case Generation for Processors Using Large Language Models (Yifei Deng,
Ren-Zhi Chen, Xiao Chao, Zhijie Yang, Yuanfeng Luo, Jingyue Zhao, Na Li,
Zhong Wan, Yongbao Ai, Huadong Dai and Lei Wang) |
| S |
Rethinking DRAM Failure
Prediction In Memory Reliability: An Efficient Deep Image Classification
Perspective (Zhishuai Han, Pijia Hao and Mufei Zhang) |
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| HW6 |
Session 7A: Advancements in Hardware Architectures (chair: Valentino Peluso) |
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| R |
NexusCIM: High-Throughput
Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores (Hyunmin Kim and
Sungju Ryu) |
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| R |
Dual-Axis ECC: Vertical and Horizontal Error Correction for Storage and Transfer Errors (Giyong Jung, Hee
Ju Na, Sang-Hyo Kim and Jungrae Kim) |
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| R |
VarVE: Bringing SIMD
Performance to Variable-width Values (Chen Zou and Andrew A. Chien) |
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| R |
Ninja: A Hardware
Assisted System for Accelerating Nested Address Translation (Longyu Zhao,
Zongwu Wang, Fangxin Liu and Li Jiang) |
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| S |
HEncode: A Highly
Modularized and Efficient FPGA QC-LDPC Encoder Using High Level Synthesis
(Jiawei Yang, Shaohua Wang, Xiangrui Yang, Yifan Zhang, Qiang Cao, Jie Yao,
Xiaodi Tan and Xiao Lin) |
| S |
Efficient Microprocessor
Design Space Exploration via Space Partitioning (Zijun Jiang and Yangdi Lyu) |
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| S |
SATL: A Spatial
Architecture Rapid Prototyping Framework for Irregular Applications
Acceleration (Francesco Peverelli, Alessandro Verosimile, Davide Conficconi,
Andrea Damiani and Marco Santambrogio) |
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| T2 |
Tutorial 2: Adaptive CNN Execution on Edge FPGAs |
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Francesco Ratto, Federico Manca and Claudio Rubattu |
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| CS2 |
Session 8A: Memory-efficient Design (chair: Yangdi Lyu) |
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| R |
VDMig: An Adaptive
Virtual Disk Migration Scheme For Cloud Block Storage System (Guangjie Xing,
Shuheng Gao, Hua Wang, Ke Zhou, Yaodong Han and Mengling Tao) |
| R |
Hermes: Memory-Efficient
Pipeline Inference for Large Models on Edge Devices (Xueyuan Han, Zinuo Cai,
Yichu Zhang, Chongxin Fan, Junhan Liu, Ruhui Ma and Rajkumar Buyya) |
| R |
Opportunistic Migration
for Hybrid memories while Mitigating Aging Effects (Aswathy N S and Hemangee
K. Kapoor) |
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| R |
HPA: A hybrid data flow
for PIM architectures (Yunping Zhao, Sheng Ma, Hengzhu Liu and Yi Dai) |
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| S |
LCKV: Learner-Cleaner Optimized Adaptive Key-Value Separated LSM-Tree Store (Mingxuan Liu,
Jianhua Gu and Tianhai Zhao) |
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| S |
LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory (Lanlan Cui, Meng Zhang and Fei Wu) |
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| SW1 |
Session 8B: SW Architectures for Optimization (chair: Vittoriano Muttillo) |
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| R |
UniCoMo: A Unified Learning-Based Cost Model for
Tensorized Program Tuning (Zihan Wang, Lei Gong, Wenqi Lou, Qianyu Cheng,
Xianglan Chen, Chao Wang and Xuehai Zhou) |
| R |
SHEEO: Continuous Energy Efficiency Optimization in Autonomous Embedded Systems Cycles
(Xinkai Wang, Chao Li, Lingyu Sun, Qizheng Lv, Xiaofeng Hou, Jingwen Leng and
Minyi Guo) |
| R |
AutoSparse: A
Source-to-Source Format and Schedule Auto-Tuning Framework for Sparse Tensor
Program (Xiangjun Qu, Lei Gong, Wenqi Lou, Qianyu Cheng, Xianglan Chen, Chao
Wang and Xuehai Zhou) |
| S |
MIST: Efficient
Mixed-Precision Preconditioning Through Iterative Sparse-Triangular Solver
Design (Haoyuan Zhang, Yidong Chen, Wenpeng Ma, Wu Yuan, Jian Zhang and
Zhonghua Lu) |
| S |
Deep Recommender Models
Inference: Automatic Asymmetric Data Flow Optimization (Giuseppe Ruggeri,
Renzo Andri, Daniele Jahier Pagliari and Lukas Cavigelli) |
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| S |
MOTPE/D: Hardware and
Algorithm Co-design for Reconfigurable Neuromorphic Processor (Yuan Li, Xun
Xiao, Ren-Zhi Chen, Zhijie Yang, Jingyue Zhao, Zhenhua Zhu, Huadong Dai,
Yuhua Tang, Weixia Xu, Li Luo and Lei Wang) |
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WEDNESDAY |
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| 9:00-10:00 |
Keynote 3: Rebuilding
AI: Hardware and Systems Approach for Next Generation AI and AGI (Eren
Kurshan, Princeton University) |
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| 10:00-11:05 |
Session 9A: EDA
for Quantum |
Session
9B: Caches |
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| 11:05-11:30 |
Coffee break |
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| 11:30-12:45 |
Session 10A: HW
Architectures for Learning |
Session
10B: Accelerators |
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| 12:45-14:15 |
Lunch break |
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| 14:15-15:20 |
Session 11A:
Energy-aware EDA |
Tutorial
3: Evolutionary Design Methods in Electronic Design Automation |
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| 15:20-16:05 |
Session 12A:
Computing Systems for Hyperdimensional Computing |
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| 16:05-16:30 |
Closing remarks & Best paper award ceremony |
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WEDNESDAY - SESSIONS
DETAILS |
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| EDA3 |
Session 9A: EDA for Quantum (chair: Serena Curzel) |
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| R |
Mera: Memory Reduction
and Acceleration for Quantum Circuit Simulation via Redundancy Exploration
(Yuhong Song, Edwin Hsing-Mean Sha, Longshan Xu, Qingfeng Zhuge and Zili
Shao) |
| R |
A Joint Optimization of
Buffer and Splitter Insertion for Phase-Skipping Adiabatic
Quantum-Flux-Parametron Circuits (Robert S Aviles and Peter A Beerel) |
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| R |
A Quantum Method to Match
Vector Boolean Functions Using Simon's Solver (Marco Venere, Alessandro
Barenghi and Gerardo Pelosi) |
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| R |
MOSQ: Accelerating
Classical Simulation of UCCSD Ansatz Circuits using Merged Operation
(Seungwoo Choi, Enhyeok Jang, Youngmin Kim and Won Woo Ro) |
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| HW3 |
Session 9B: Caches (chair: Lukas Sekanina) |
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| R |
AceMiner: Accelerating
Graph Pattern Matching using PIM with Optimized Cache System (Liang Yan,
Xiaoyang Lu, Xiaoming Chen, Sheng Xu, Xingqi Zou, Yinhe Han and Xian-He Sun) |
| R |
Hardware Cache Locking
for All Memory Updates (Ashkan Asgharzadeh, Eduardo José Gómez-Hernández,
Juan M. Cebrian, Stefanos Kaxiras and Alberto Ros) |
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| R |
CacheTrimmer: Adaptive
Cache File Trimming for Optimized Performance and Lifetime on Mobile Devices
(Yi Zhang, Yunpeng Song, Wentong Li, Yiyang Huang, Dingcui Yu, Mengyang Ma
and Liang Shi) |
| R |
CCacheSim: A
Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based In-Cache
Computing System Evaluation (Baiqing Zhong, Mingyu Wang, Yicong Zhang,
Xiaojie Li and Zhiyi Yu) |
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| HW5 |
Session 10A: HW Architectures for Learning (chair: Seon Kim) |
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| R |
VEGA: Implementing a
Versatile and Efficient Deep Learning Processor with Graph-Based ALU
(Wenqiang Wang, Yuzhou Chen, Guanting Huo, Guanghui He and Ningyi Xu) |
| R |
FloatMax: An Efficient
Accelerator for Transformer-based Models exploiting Tensor-wise Adaptive
Floating-Point Quantization (Seo-Ho Chung, Kwangrae Kim, Soo-Min Rho,
Chan-Hoon Kim and Ki-Seok Chung) |
| R |
EN-T: Optimizing Tensor
Computing Engines Performance via Encoder-Based Methodology (Qizhe Wu, Yuchen
Gui, Zhichen Zeng, Xiaotian Wang, Huawen Liang and Xi Jin) |
| S |
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations (Vittoriano Muttillo,
Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante and Daniele
Frigioni) |
| S |
Dystar-GNN: A Dynamic and
Sparsity-Oriented Accelerator for Enhanced Graph Neural Network Execution
(Jiaqi Yang, Hao Zheng and Ahmed Louri) |
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| S |
Early: An Importance-aware Early Firing and Exit for SNN Acceleration (Xuan Zhang, Zhuoran
Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang,
Naifeng Jing and Xiaoyao Liang) |
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| CS3 |
Session 10B: Accelerators (chair: Flavio Ponzina) |
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| R |
Vision Transformer
Inference on a CNN Accelerator (Changjae Yi, Hyunsu Moh and Soonhoi Ha) |
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| R |
WOLT: Transparent
Deployment of ML Workloads on Lightweight Many-Accelerator Architectures
(Kuan-Lin Chiu, Guy Eichler, Chuan-Tung Lin, Giuseppe Di Guglielmo and Luca
Carloni) |
| R |
AirGun: Adaptive
Granularity Quantization for Accelerating Large Language Models (Sungbin Kim,
Hyunwuk Lee, Sungwoo Kim, Cheolhwan Kim and Won Woo Ro) |
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| R |
TileMap: Mapping
Multi-Head Attention on Spatial Accelerators with Tile-based Analysis (Fuyu
Wang and Minghua Shen) |
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| S |
ISVDA: An In Storage
Processing Accelerator for Visual Data Analysis (Zhenhua Zhao, Zhaoyan Shen
and Xiaojun Cai) |
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| EDA1 |
Session 11A: Energy-aware EDA (chair: Mattia Tibaldi) |
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| R |
Simultaneous Conjugate
Gradient and iAFF-UNet for Accurate IR Drop Calculation (He Liu, Yipei Xu,
Simin Tao, Zhipeng Huang, Biwei Xie, Xingquan Li and Wei Gao) |
|
| R |
Global and Local
Attention-based Inception U-Net for Static IR Drop Prediction (Yilu Chen,
Zhijie Cai, Min Wei, Zhifeng Lin and Jianli Chen) |
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|
| S |
A Prototype-Based
Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
(Gabriele Montanaro, Andrea Galimberti and Davide Zoni) |
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| S |
A Methodology for Fast
and Efficient ML-Based Power Modeling (Caaliph Andriamisaina, Kods Trabelsi
and Pierre-Guillaume Le Guay) |
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| T3 |
Tutorial 3: Evolutionary
Design Methods in Electronic Design Automation |
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Lukas Sekanina |
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| CS5 |
Session 12A: Computing Systems for Hyperdimensional Computing (chair: Luca Bertaccini) |
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| R |
Multi-Model Inference Composition of Hyperdimensional Computing Ensembles (Flavio Ponzina,
Rishikanth Chandrasekaran, Vivian Wang, Seiji Minowada, Siddharth Sharma and
Tajana Rosing) |
| R |
Integrating Branching and
Pruning for Efficient Hyperdimensional Computing (Jing Liu, Zhiqian Guan, Di
Liu, Shengfa Miao and Fei Dai) |
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| R |
Efficient Forward-Only
Training for Brain-Inspired Hyperdimensional Computing (Hyunsei Lee, Jiseung
Kim, Seohyun Kim, Hyukjun Kwon, Mohsen Imani, Ilhong Suh and Yeseong Kim) |
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