ICCD 2019


Important Dates:

Abstract Submission
21-June-2019, 11:59pm AOE
28-June-2019, 11:59pm AOE(Extended)

Paper Submission
28-June-2019, 11:59pm AOE
7-July-2019, 11:59pm AOE(Extended)

Notification
9-Sept-2019

Camera-Ready
30-Sept-2019

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Web Chair

2019 IEEE International Conference on Computer Design (ICCD)

 

Technical Program

The durations are: 17+3 minutes for Regular Papers (R), 8+2 minutes for Short Papers (S), and 12+3 minutes for Invited Papers (I). 3 and 2 minutes are the Q&A part.

Note: The tutorials are open to all registered conference attendees at no additional cost.

Note: Papers highlighted with a (*) are best paper candidates.

Sunday, November 17, 2019
14:00-18:00 Tutorial 1 (Room 1A, Entrance# 001A, 001B):  Baker Mohammad, Heba Abunahla, Yasmin Halawani. RRAM Technology for Efficient In-Memory Computing Architectures and Applications. Tutorial 2 (Room 1C, Entrance# 003A, 003):  Davide Patti. Estimation Tools for Wireless On-Chip Networks with an Application to Approximated Deep Neural Network Inference.
18:00-18:30 Coffee Break (Location: MPR Hallway)
18:30-20:00

Keynote 1: Innovation after Moore's Law, by Dr. Rob Aitken (Arm Research)

Session Chair: Miroslav Velev
(Location: Lecture Hall (Room 007))

Monday, November 18, 2019
07:30-08:00 Registration/Breakfast (Location: Lower Atrium)
08:00-08:30 Opening Session
08:30-09:30

Keynote 2: Towards Bridging the Gap between Hardware and Software Security, by Professor Thorsten Holz (Ruhr-University Bochum)

Session Chair: Mihalis Maniatakos
(Location: Lecture Hall (Room 007))

09:30-10:50 Session 1A: Optimized design methodology (Room 1A, Entrance# 001A, 001B) Session 1B: Accelerators and Machine Learning I (Room 1C, Entrance# 003A, 003)
Session Chair: Yiorgos Makris Session Chair: Ben Carrion Schaefer
12 (R) Ilias Giechaskiel, Kasper Rasmussen and Jakub Szefer. Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs 144 (R) Guy Maor, Xiaoming Zeng, Zhendong Wang and Yang Hu. An FPGA Implementation of Stochastic Computing-based LSTM
162(*) (R) Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding and Shawn Blanton. IPSA: Integer Programming via Sparse Approximation for Efficient Test-chip Design 35 (R) Maodi Ma, Jingweijia Tan, Xiaohui Wei and Kaige Yan. Process Variation Mitigation on Convolutional Neural Network Accelerator Architecture
351 (R) Prashanth Krishnamurthy, Hossein Salehghaffari, Shiva Duraisamy, Ramesh Karri and Farshad Khorrami. Stealthy Rootkits in Smart Grid Controllers 13 (R) Yunfan Li, Drew Penney, Abhishek Ramamurthy and Lizhong Chen. Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning Approach
376 (R) Chiou-Yng Lee and Jiafeng Xie. Efficient Scalable Three Operand Multiplier over $GF(2^m)$ based on Novel Decomposition Strategy 112 (R) Jinrong Guo, Wantao Liu, Wang Wang, Chunrong Yao, Jizhong Han, Ruixuan Li, Yijun Lu and Songlin Hu. AccUDNN: A GPU Memory Efficient Accelerator for Training Ultra-deep Neural Networks
10:50-11:10 Coffee Break (Location: MPR Hallway)
11:10-12:30 Session 2A: Architectural Advances for IoT Applications (Room 1A, Entrance# 001A, 001B) Session 2B: Architecture & Compilers II (Room 1C, Entrance# 003A, 003)
Session Chair: Chun-Yi Lee Session Chair: Paul V. Gratz
26 (R) Hsuan-Kung Yang, Tsu-Jui Fu, Po-Han Chiang, Kuan-Wei Ho and Chun-Yi Lee. A Distributed Scheme for Accelerating Semantic Video Segmentation on An Embedded Cluster 22 (R) Mainak Chaudhuri, Jayesh Gaur and Sreenivas Subramoney. Bandwidth-aware Last-level Caching: Efficiently Coordinating Off-chip Read and Write Bandwidth
36 (R) Heejong Park, Arvind Easwaran and Sidharta Andalam. TiLA: Twin-in-the-Loop Architecture for Cyber-Physical Production Systems 45 (R) Vinson Young and Moinuddin Qureshi. To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
232(*) (R) Wen Li, Ying Wang, Huawei Li and Xiaowei Li. RRAMedy: Protecting ReRAM-based Neural Network from Permanent and Soft Faults During Its Lifetime 213 (R) Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca Carloni and Laura Pozzi. Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
3 (R) Junichiro Kadomoto, Hidetsugu Irie and Shuichi Sakai. WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers

51 (R) En Shao, Guangming Tan and Ninghui Sun. A new traffic offloading method with slow switching optical device in exascale computer

12:30-13:30 Lunch
13:30-14:50 Session 3A: Advances in the Design and Implementation of Neural Networks (Room 1A, Entrance# 001A, 001B) Session 3B: Storage Systems (Room 1C, Entrance# 003A, 003)
Session Chair: Manu Perumkunnil Session Chair: Zia Abbas
117(*) (R) Bing Wu, Dan Feng, Wei Tong, Jingning Liu, Chengning Wang, Wei Zhao and Mengye Peng. ReRAM Crossbar-based Analog Computing Architecture for Naive Bayesian Engine 38 (R) Ming-Chang Lee, Li-Pin Chang, Sung-Ming Wu and Wei-Shang Yui. Adaptive Write Interference Management with Efficient Mapping for Shingled Recording Disks
261 (R) S. Rasoul Faraji, Singh Gaurav and Kia Bazargan. HBUNN - Hybrid Binary-Unary Neural Network - Realizing a complete CNN on an FPGA 80 (R) Chunxue Zuo, Fang Wang, Ping Huang, Yuchong Hu and Dan Feng. RepEC-Duet: Ensure High Reliability and Performance for Deduplicated and Delta-Compressed Storage Systems
63 (R) Shenggang Chen and Zhonghai Lu. Hardware Acceleration of Multilayer Perceptron Based on Inter-layer Optimization 116 (R) Tianming Jiang, Jiangfeng Zeng, Ke Zhou, Ping Huang and Tiangming Yang. Lifelong Disk Failure Prediction via GAN-based Anomaly Detection
238 (S) Gaoming Du, Zhengwen Yang, Zhenmin Li, Duoli Zhang, Yong-Sheng Yin and Zhonghai Lu. NR-MPA: Non-Recovery Compression based Multi-path Packet-connected-circuit Architecture of Convolution Neural Networks Accelerator

371 (R) Yubo Liu, Hongbo Li, Yutong Lu, Zhiguang Chen and Ming Zhao. An Efficient and Flexible Metadata Management Layer for Local File Systems

43 (S) Xiaojia Song, Tao Xie and Stephen Fischer. A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLS
14:50-15:10 Coffee Break (Location: MPR Hallway)
15:10-16:30 Session 4A: Innovation on Safety and Security for Robust Real-Time Systems (Room 1A, Entrance# 001A, 001B) Session 4B: Processor and Memory Architectures (Room 1C, Entrance# 003A, 003)
Session Chair: Farshad Khorrami Session Chair: Manoranjan Satpathy
151 (R) Hengyi Liang, Zhilu Wang, Debayan Roy, Soumyajit Dey, Samarjit Chakraborty and Qi Zhu. Security-driven Codesign with Weakly-hard Constraints for Real-time Embedded Systems 209 (R) Timon Evenblij, Manu Perumkunnil, Nicolas Bueno, Jose Ignacio Gomez-Perez, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnemont, Christian Tenllado and Francky Catthoor. A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
100 (R) Sergi Vilardell, Isabel Serra, Jaume Abella, Joan Del Castillo and Francisco J Cazorla. Software Timing Analysis for Complex Hardware with Survivability and Risk Analysis 90 (R) Jonathan Beaumont and Trevor Mudge. Dynamically Managing Resources for Irregular Parallelism
208 (R) Xiaochen Hao, Mingsong Lv, Jiesheng Zheng and Wang Yi. Integrating Cyber Attack Defense Technique into Real-Time Cyber-Physical Systems 18 (R) Pooria M. Yaghini, George Michelogiannakis and Paul V. Gratz. SpecLock: Speculative Lock Forwarding
173 (R) Moming Duan, Duo Liu, Xianzhang Chen, Yujuan Tan, Jinting Ren, Lei Qiao and Liang Liang. Astraea: Self-balancing Federated Learning for Improving Classification Accuracy of Mobile Deep Learning Applications 368 (R) Nezam Rohbani, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch and Hirotaka Takatsuka. NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache
16:30-16:35 Room Switching Break
16:35-17:20 Session 5A: IoT covert channel attacks in air-gapped networks (Room 1A, Entrance# 001A, 001B) Session 5B: Miscellaneous topics in Test, Verification, and Security (Room 1C, Entrance# 003A, 003)
Session Chair: Christina Pöpper Session Chair: Jiafeng (Harvest) Xie
389 (I) Ryan Vrecenar, Micheal Hall, Josh Zshiesche, Mahesh Naidu, Jeyavijayan Rajendran, Stavros Kalafatis. Red Teaming a Multi-colored Bluetooth Bulb

156 (S) Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy and Madhu Mutyam. Post-Model Validation of Victim DRAM Caches

382 (I) Eleonore Carpentier, Corentin Thomasset, Jeremy Briffaut. Bridging the gap: Data exfiltration in highly secured environments using Bluetooth IoTs

248 (S) Mohammad-Mahdi Bidmeshki, Kiruba Sankaran Subramani and Yiorgos Makris. Revisiting Capacitor-Based Trojan Design and Detection

383 (I) Patrick Cronin, Charles Gouert, Dimitrios Mouris, Nektarios Georgios Tsoutsos, Chengmo Yang. Covert Data Exfiltration Using Light and Power Channels

303 (S) Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy and Srinivas Pinisetty. Formal Modeling and Verification of NAND Flash Memory supporting Advanced Operations

Tuesday, November 19, 2019
08:00-08:30 Breakfast (Location: Lower Atrium)
08:30-09:30

Keynote 3: Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation, by Professor Onur Mutlu (ETH Zurich)

Session Chair: Ozgur Sinanoglu
(Location: Lecture Hall Room 007)

09:30-10:50 Session 6A: Hardware and software implementations for efficient post quantum cryptography (Room 1A, Entrance# 001A, 001B) Session 6B: Architecture & Compilers I (Room 1C, Entrance# 003A, 003)
Session Chair: Ramesh Karri Session Chair: Jan Moritz Joseph
386 I) Sujoy Sinha Roy.  SaberX4: High-throughput Software Implementation of Saber Key Encapsulation Mechanism 46 (R) Vinson Young, Zeshan Chishti and Moinuddin Qureshi. TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems
381 (I) Emanuele Bellini, Florian Caullery, Rusydi Makarim, Marc Manzano, Chiara Marcolla and Victor Mateu.  Advances and Challenges of Rank Metric Cryptography Implementations 176 (R) Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Static Function Prefetching for Efficient Code Management on Scratchpad Memory
385 (I) Hamid Nejatollahi, Rosario Cammarota and Nikil Dutt. Flexible NTT Accelerators for RLWE Lattice-Based Cryptography 149 (R) Jianqi Chen and Benjamin Carrion Schafer. Low Power Design through Frequency-Optimized Runtime Micro-architectural Adaptation

384 (I) Huili Chen, Rosario Cammarota, Felipe Valencia and Francesco Regazzoni. PlaidML-HE: Acceleration of Deep Learning Kernels to Compute on Encrypted Data

62 (R) Zhuohui Duan, Haikun Liu, Xiaofei Liao, Hai Jin, Wenbin Jiang and Yu Zhang. HiNUMA: NUMA-aware Data Placement and Migration in Hybrid Memory Systems
388 (I) Deepraj Soni, Mohammed Nabeel, Kanad Basu and Ramesh Karri. Power, Area, Speed, and Security (PASS) Trade-offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow
10:50-11:10 Break
11:10-12:40 Session  7A: Advances in Power, Thermal and Timing Aware Optimization (Room 1A, Entrance# 001A, 001B) Session  7B: EDA for Non-Logic Issues and Non-CMOS Technologies (Room 1C, Entrance# 003A, 003)
Session Chair: Timon Evenblij Session Chair: Xiaoming Chen
346 (R) Behnam Khaleghi, Sahand Salamat, Mohsen Imani and Tajana Rosing. FPGA Energy Efficiency by Leveraging Thermal Margin 34 (R) Inga Abel, Maximilian Neuner and Helmut Graeb. Constraint-Programmed Initial Sizing of Analog Operational Amplifiers
110 (R) Mohammed Salman Ahmed and Zia Abbas. A Memetic Algorithm based PVT Variation-aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design 66 (R) Ling-Yen Song, Yi-Ling Chen, Yung-Chun Lei and Juinn-Dar Huang. Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs
347 (R) Mohammad Saeed Abrishami, Massoud Pedram and Shahin Nazarian. CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach 309 (R) Ruizhe Cai, Olivia Chen, Ao Ren, Ning Liu, Nobuyuki Yoshikawa and Yanzhi Wang. A Buffer and Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
135 (S) Jianqi Chen and Benjamin Carrion Schafer. Exploiting the Benefits of High-level Synthesis for Thermal-aware VLSI Design 76 (R) Cheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan, Christopher Torng, Shady Agwa and Christopher Batten. PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Interconnection Networks
193 (S) Charalampos Antoniadis, Milan Mihajlović, Nestor Evmorfopoulos, Georgios Stamoulis and Vasilis Pavlidis. Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits 338 (S) Shahin Nazarian, Arash Fayyazi and Massoud Pedram. qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework
41 (S) Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto Garcia-Ortiz and Thilo Pionteck. System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips
12:40-15:00 Lunch + Poster Session (Location: Lower Atrium)
15:00- Social Event: Safari (Location: Upper Atrium, Installation Zone)
Wednesday, November 20, 2019
08:00-08:30 Breakfast (Location: Lower Atrium)
08:30-09:30

Keynote 4: Embedded Encryption and Machine Learning technologies for IoT Security, by Dr. Najwa Aaraj (UAE Technology Innovation Institute)

Session Chair: Hoda Al Khzaimi
(Location: Lecture Hall Room 007)

09:30-10:50 Session  8A: Robust hardware design with machine learning (Room 1A, Entrance# 001A, 001B) Session  8B: Accelerators and Machine Learning II (Room 1C, Entrance# 003A, 003)
Session Chair: Rajat Subhra Chakraborty Session Chair: Virendra Singh
88 (R) Yongjian Li, Jialun Cao and Jun Pang. A Learning-based Framework for Automatic Parameterized Verification 150 (R)Wen Wen, Youtao Zhang and Jun Yang. ReNEW: Enhancing Lifetime for ReRAM Crossbar based Neural Network Accelerators
128 (R) Farah Naz Taher, Anjana Balachandran and Benjamin Carrion Schafer Learning-based Diversity Estimation: Leveraging the Power of High-le.vel Synthesis to mitigate Common-mode Failure 82 (R) Weihao Cui, Mengze Wei, Quan Chen, Xiaoxin Tang, Jingwen Leng, Li Li and Minyi Guo. Ebird: Elastic Batch for Improving Responsiveness and Throughput of Deep Learning Services
134 (R) Avishek Choudhury and Biplab K Sikdar. Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model based Reusability Predictor 49 (R) Ning Lin, Hang Lu, Xing Hu, Jingliang Gao, Mingzhe Zhang and Xiaowei Li When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices
186 (R) Young Seo Lee, Kyung Min Kim, Ji Heon Lee, Jeong Hwan Choi and Sung Woo Chung. A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication
10:50-11:10 Break (Location: MPR Hallway)
11:10-12:30 Session  9A: Innovative Circuits for Improved Power Consumption and Performance Characteristics (Room 1A, Entrance# 001A, 001B) Session 9B: Hardware security  (Room 1C, Entrance# 003A, 003)
Session Chair: Ann Gordon Ross Session Chair: Johann Knechtel
139 (R) Siyuan Xu and Benjamin Carrion Schafer. Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations 298 (R) Maxime Montoya, Thomas Hiscock, Simone Bacles-Min, Anca Molnos and Jacques Fournier.  Adaptive Masking: a Dynamic Trade-off between Energy Consumption and Hardware Security
344 (R) Divya Pathak and Ioannis Savidis. Applying swarm intelligence to distributed on-chip power management 85 (R) Saranyu Chattopadhyay and Rajat Subhra Chakraborty. Cyclic Beneš Network based Logic Encryption for Mitigating SAT-Based Attacks
9 (R) Xiaoyu Zhang, Xiaoming Chen and Yinhe Han. FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-based Memory Array 98 (R) Mahmood Azhar Qureshi and Arslan Munir. PUF-RLA: A PUF-based Reliable and Lightweight Authentication Protocol employing Binary String Shuffling
140 (R) Ankit Wagle, Gian Singh, Jinghua Yang, Sunil Khatri and Sarma Vrudhula. Threshold Logic in a Flash 55 (R) Jingquan Ge, Neng Gao, Chenyang Tu, Ji Xiang and Zeyi Liu. AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based Cache Attacks on ARM-FPGA Embedded SoC
12:30-13:30 Lunch (Location: Lower Atrium)
13:30-14:50 Session 10A: Miscellaneous Topics in Computer Systems I (Room 1A, Entrance# 001A, 001B) Session 10B: Machine Learning Techniques for Innovative Energy-Efficient Solutions (Room 1C, Entrance# 003A, 003)
Session Chair: Sarma Vrudhula Session Chair: Ioannis Savidis
143 (R) Jianda Wang and Yang Hu. Architectural and Cost Implications of the 5G Edge NFV Systems 5 (R) Ruben Vazquez, Ann Gordon-Ross and Greg Stitt. Energy Prediction for Cache Tuning in Embedded Systems
93 (R) Yuezhi Che, Yuan Hong and Rujia Wang. Imbalance-aware scheduler for fast and secure Ring ORAM data retrieval 14 (R) Shaswot Shresthamali, Masaaki Kondo and Hiroshi Nakamura. Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning
37 (R) Wenhui Zhang, Qiang Cao, Hong Jiang, Jie Yao, Yuanyuan Dong and Puyuan Yang. SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance 138 (R) Kazim Ergun, Raid Ayoub, Pietro Mercati and Tajana Rosing. Dynamic Optimization of Battery Health in IoT Networks
292 (S) Jinghan Zhang, Hamed Tabkhi and Gunar Schirner. Mitigating Application Diversity for Allocating a Unified ACC-Rich Platform 243 (S) Matina Maria Trompouki and Leonidas Kosmidis. BRASIL: A High-Integrity GPGPU Toolchain for Automotive Systems.
50 (S) Ning Lin, Hang Lu, Jingliang Gao, Shunjie Qiao and Xiaowei Li. VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation
14:50-15:10 Break
15:10-16:00 Session 11A: Miscellaneous Topics in Computer Systems II (Room 1A, Entrance# 001A, 001B) Session 11B:  Processor and memory architectures (Room 1C, Entrance# 003A, 003)
Session Chair: Ankit Wagle Session Chair: Cheng Tan
181 (S) Mingzhe Zhang, Lunkai Zhang, Frederic Chong and Zhiyong Liu. Balancing Performance and Energy Efficiency of ONoC by Using Adaptive Bandwidth 297 (R) Wonjun Song and John Kim. A Case for Software-based Adaptive Routing in NUMA systems
184 (S) Lanlan Cui, Fei Wu, Xiaojian Liu, Meng Zhang and Changsheng Xie. VaLLR: ThReshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash 64 (S) Kleovoulos Kalaitzidis and Andre Seznec. Value Speculation through Equality Prediction
68 (S) Yicheng Wang, Yang Liu, Peiyun Wu and Zhao Zhang. Reinforce Memory Reliability Under Row Hammering Attack by Breaking DRAM Disturbance Correlation Within ECC Words 157 (S) Donghyun Kang, Jintaek Kang, Hyungdal Kwon, Hyunsik Park and Soonhoi Ha. A Novel CNN (Convolutional Neural Network) Accelerator That Enables Fully-pipelined Execution of Layers.
182 (S) Jingting Ren, Xianzhang Chen, Yujuan Tan, Duo Liu, Moming Duan, Liang Liang and Lei Qiao. Archivist: A Machine Learning Assisted Data Placement Mechanism for Hybrid Storage Systems 183 (S) Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat and Virendra Singh. Freeflow Core: Enhancing Performance of In-order Cores with Energy Efficiency
267 (S) Yi Zhang, Zhanwei Ling, Ran Cui, Mingsong Lv, Nan Guan and Qingxu Deng. Detecting and Predicting Performance Degradation Caused by Impaired Cache Isolation
16:00-

City tour - Conference Dinner (Meetup Location: A6 Main Entrance)