ICCD 2019 - Organizing Committee

ICCD 2019

    Important Dates:

    Abstract Submission
    21-June-2019, 11:59pm AOE
    28-June-2019, 11:59pm AOE(Extended)

    Paper Submission
    28-June-2019, 11:59pm AOE
    7-July-2019, 11:59pm AOE(Extended)



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    Web Chair

37th IEEE International Conference on Computer Design (ICCD'19)

Thorsten Holz

Professor in the Faculty of Electrical Engineering and Information Technology at Ruhr-University Bochum, Germany

Title: Towards Bridging the Gap between Hardware and Software Security

Abstract: Attackers have to overcome more and more obstacles to exploit a vulnerability in a given application because defense mechanisms such as stack protections, data-execution prevention (DEP), address space layout randomization (ASLR) and control-flow integrity (CFI) are nowadays widely deployed. Modern defenses often require that an attacker adapts her exploit to the current state of the application she is attacking. For this reason, many modern exploits target browsers or PDF readers, which come with a built-in scripting engine. Another important attack vector are side channels given that they enable an attacker to leak sensitive information about the system. In this talk, we will review recent advances in these areas and outline how computer designers and software security researchers can collaborate to address open challenges to stop even advanced attackers.


Thorsten Holz is a professor in the Faculty of Electrical Engineering and Information Technology at Ruhr-University Bochum, Germany. His research interests include technical aspects of secure systems, with a specific focus on systems security. Currently, his work concentrates on reverse engineering, automated vulnerability detection, and studying latest attack vectors. He received the Dipl.-Inform. degree in Computer Science from RWTH Aachen, Germany (2005), and the Ph.D. degree from University of Mannheim (2009). Prior to joining Ruhr-University Bochum in April 2010, he was a postdoctoral researcher in the Automation Systems Group at the Technical University of Vienna, Austria. In 2011, Thorsten received the Heinz Maier-Leibnitz Prize from the German Research Foundation (DFG) and in 2014 an ERC Starting Grant. Furthermore, he is Co-Spokesperson of the Cluster of Excellence "CASA - Cyber Security in the Age of Large-Scale Adversaries" (with C. Paar and E. Kiltz).


Onur Mutlu

Professor of Computer Science at ETH Zurich

Title: Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation

Abstract: Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks: 1) data access from memory is already a key bottleneck as applications become more data-intensive and memory bandwidth and energy do not scale well, 2) energy consumption is a key constraint in especially mobile and server systems, 3) data movement is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, and intelligent memory controllers to solve the RowHammer problem are an evidence of this trend. In this talk, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, applications, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms and real data-intensive applications, spanning machine learning, graph processing, data analytics, and genome analysis, at low cost. If time permits, we will also discuss and describe simulation and evaluation infrastructures that can enable exciting and forward-looking research in future memory systems, including Ramulator and SoftMC.


Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.


Najwa Aaraj

Chief Scientist at the UAE Technology Innovation Institute (TII)

Title: Embedded Encryption and Machine Learning technologies for IoT Security

Abstract: IoT devices are increasingly being deployed for a multitude of functionalities, covering smart cities and critical infrastructure. Such devices are inherently insecure, with security being thought through in the aftermaths of mass deployments. Furthermore, the diverse range of such embedded devices, coupled with their energy constrained nature and the lack of cryptographic and security standards makes IoT vulnerabilities even more pronounced. In this talk, we cover at a high level embedded cryptographic technologies and lightweight primitives and protocols applied to embedded systems. We also explore use cases of applying machine learning to address security concerns in IoT devices.


Dr Najwa Aaraj is a Chief Scientist at the UAE Technology Innovation Institute (TII). Dr. Najwa's expertise lies in applied cryptography, trusted platforms, security architecture for embedded systems, software exploit detection and prevention systems, and biometrics. She has over 15 years of experience working in the United States, Australia, the Middle East, Africa and Asia with global firms. Dr Najwa holds a PhD in Computer Engineering and a Master of Science Degree in Computer and Information Systems Security from Princeton University. She holds a bachelor's degree in Computer and Communications Engineering from the American University in Beirut. She has a multitude of patents and publications in the fields of embedded security, applied cryptography and has found a new area of focus on Machine Learning applied to security technologies. Prior to joining TII, Dr. Najwa worked in DarkMatter, Booz & Company, where she led consulting engagements in the communication and technology industry for clients across four continents. Previously, she held several research positions including Research Fellow with IBM T. J. Watson Security Research in New York, and with the Intel Security Research Group in Portland, Oregon. She was also a Research Staff Member at NEC Laboratories in Princeton, New Jersey.


Rob Aitken

Arm Fellow and technology lead for Arm Research

Title: Innovation after Moore's Law


Abstract: Gordon Moore observed decades ago that the number of circuits that can be placed on a computer chip doubles every two years. His observation, dubbed Moore's Law, has served the electronics industry well, allowing a steady stream of products with better features, performance and cost, but over the last few years delays in release of new manufacturing technologies, skyrocketing chip development costs, along with rapidly approaching physical limits, show that progress is definitely slowing, and may be stopping. While this may seem worrisome to technologists and designers who have spent their entire careers riding the productivity wave that Moore's Law created, it simultaneously opens up exciting opportunities for innovation in chip design, architecture and manufacturing. These opportunities can in turn lead to even more exciting new products. This talk looks at the current state of chip technology, how we got here, and most importantly where we might go next.


Rob Aitken is an Arm Fellow and technology lead for Arm Research. He is responsible for technology direction of Arm research, including identifying disruptive technologies, monitoring the global technology landscape, and coordinating research efforts within and outside of Arm. His role includes developing strategic relationships with universities, consortia, and other key participants in the global research community. His research interests include emerging technologies, memory design, design for variability, resilient computing, and statistical design. He has published over 80 technical papers on a wide range of topics including impacts of technology scaling, statistics of memory bit cell variability and the use of static current monitoring as a circuit testing and diagnostic mechanism. He holds over 30 US patents. Dr. Aitken joined Arm as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given keynote addresses, tutorials and short courses at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and served as General Chair for the 2019 Design Automation Conference.