ICCD 2019

Important Dates:

Abstract Submission
21-June-2019, 11:59pm AOE
28-June-2019, 11:59pm AOE(Extended)

Paper Submission
28-June-2019, 11:59pm AOE



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37th IEEE International Conference on Computer Design 

November 17 - 20, 2019

Abu Dhabi, United Arab Emirates (U.A.E.)

New York University – Abu Dhabi Campus

Keynote Speakers

Keynote 1: Professor Thorsten Holz (Ruhr-University Bochum)

Keynote 2: Professor Onur Mutlu (ETH Zurich)

Keynote 3: Dr. Najwa Aaraj (DarkMatter Group)

Keynote 4: Dr. Rob Aitken (Arm Research)


The IEEE International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology. We especially encourage submissions that look forward to future systems and technologies.
The theme for ICCD'19 is cybersecurity.
Original manuscripts are welcomed to be submitted to the following tracks:
Track 1. Computer Systems: Systems architecture (memory hierarchy, memory, storage, NoC), and systems software (compiler, programming language/model, OS, hypervisor, runtime) design and co-design for embedded/real-time systems, high-performance computing (HPC) systems, data center and cloud/edge servers, exascale systems; General purpose multi/many cores, co-processors, accelerators, and application-specific systems; Support for security, reliability, and energy efficiency and proportionality; Architectures and compilers for thread parallelism, synchronization, and communication; Virtual memory; Systems support for NVMs and future novel computing platforms including quantum, neuromorphic, and bio-inspired computing; Specialized OS, runtime, and storage systems for high-performance computing and exascale systems.
Track 2. Electronic Design Automation: System-level design and synthesis; High-level, logic and physical synthesis; Physical planning, design, and early estimation for large circuits; Automatic analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including floorplanning, placement, and routing; Clock-tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC methodologies; Tools and design methods for emerging technologies (MEMs, spintronics, nano, quantum).
Track 3. Embedded Systems and IoT: All aspects of embedded systems, and IoT devices; Ubiquitous computing, and sensing; Cloud computing; Wireless sensor networks; RFID; Data collection, and information management; Digital control; Man-machine interaction; Plant automation systems, and optimal resource allocation; Factory of the future; IoT sensors for supply-chain management; Blockchain for enterprise resource planning, and supply-chain management; Safety, maintainability, and availability; Fail-safe vs. fail-operational; Smart environments; Smart water; Smart energy, and smart grid; Smart homes; Smart driving, smart traffic; Pervasive sensing, and control devices; Linking the cyber and biological worlds; Brain-machine interfaces; Body-area networks; Wireless implanted interfaces.
Track 4. Logic and Circuit Design: Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMs, nano-spintronics, quantum, flexible electronics, multigate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits.
Track 5. Processor Architecture: Microarchitecture design techniques for single- and multi-core processors, such as instruction-level parallelism, pipelining, caching, branch prediction, and multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, application-specific and digital signal processor design; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, postmortems.
Track 6. Test, Verification, and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives; Side-channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.

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