IEEE Women in Engineering Committee Workshop at ICCD 2015
WEDNESDAY OCTOBER 21st 13:00-16:00
Organizers: Eren Kursun, Ann Gordon-Ross
  Sunday, October 18th 83 regular papers, 3 special sessions with 3 papers each
13:10~ Tutorial 1:  Synthesis and Verification of Arithmetic Circuits 
Organizers: Luca Amaru (EPFL), Maciej Ciesielski (University of Massachusetts, Amherst), Pierre-Emmanuel Gaillardon (EPFL) and Giovanni De Micheli (EPFL)
Speakers: Luca Amaru (EPFL), Maciej Ciesielski (University of Massachusetts, Amherst)
Tutorial 2: Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation
Organizers: Mark Hempstead (Tufts University), Baris Taskin (Drexel University)
Speakers: Baris Taskin (Drexel University), Mark Hempstead (Tufts University), Michael Lui (Drexel University), Stephan Diestelhorst (ARM Research)
  Monday. October 19th
08:00-08:30 Breakfast
08:30-10:00 Opening & Keynote
10:00-10:20 Break
10:20-11:40 CSA  1 : NOC Design TVS 1 : Verification
  Session Chair: Paul Gratz, Texas A&M University Session Chair: Masahiro Fujita, University of Tokyo Room Legend
  1. 94-Elena Kakoulli, Vassos Soteriou, Charalambos Koutsides and Kyriacos Kalli. Design of High-Performance, Power-Efficient Optical NoCs Using Silica-Embedded Silicon Nanophotonics;   1. (387) Vijay Kiran Kalyanam, Martin Saint-Laurent and Jacob Abraham. Power-Aware Multi-Voltage Custom Memory Models for Enhancing RTL and Low Power Verification;  NYU Abu Dhabi, 19 Washington Square
  2.(287)  Jiashen Li and Yun Pan. A Fast and Energy Efficient Branch and Bound Algorithm for NoC Task Mapping' 2. (111) Djordje Maksimovic, Andreas Veneris and Zissis Poulos. Clustering-based Revision Debug in Regression Verification;  Kimmel Center, Eisner and Lubin Auditorium
  3. (126) Cunlu Li and Dezun Dong. RoB-Router : Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer;  3. (144) Prateek Puri and Michael Hsiao. SI-SMART: Functional Test Generation for RTL Circuits Using Loop Abstraction and Learning Recurrence Relationships; Checkers for Post-Silicon Validation Kimmel Center, 405
  4. (120)  Dharanidhar Dang, Rabi Mahapatra and Ej Kim. PID Controlled Thermal Management of Photonic Network-on-Chip 4. (264) Pouya Taatizadeh and Nicola Nicolici. Emulation-Based Selection and Assessment of Assertion  Kimmel Center, 406
11:45-13:05 CSA2: Energy and Performance Optimization   EDA1: Error and Fault Tolerant Circuits 
  Session Chair: Mingoo Seok, Columbia University Session Chair: Donatella Sciuto, Politecnico di Milano, Italy
  1. (249) Karthikeyan P. Saravanan, Paul Carpenter and Alex Ramirez. Exploring multiple sleep modes in On/Off based Energy Efficient HPC Networks;  1.(60)  Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii and Massimo Poncino. An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy; 
  2. (197) Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana and Houman Homayoun. Wide I/O or LPDDR? Exploration and Analysis of Performance, Power and Temperature Trade-offs of Emerging DRAM Technologies in Embedded MPSoCs;  2.(110)  Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki and Tomoo Inoue. Logic Simplification by Minterm Complement for Error Tolerant Application; 
  3. (166) David Penry. Improving the Interface Performance of Synthesized Structural FAME Simulators through Scheduling;  3. (328)  Alvaro Velasquez and Sumit Kumar Jha. Fault-Tolerant Crossbar Computing using Path Enumeration; 
  4. (336) Michael Hall and Roger Chamberlain. Using M/G/1 Queueing Models with Vacations to Analyze Virtualized Logic Computations 4.(282)  Ali Ahari, Mojtaba Ebrahimi, Fabian Oboril and Mehdi Tahoori. Improving Reliability, Performance, and Energy Efficiency of STT-MRAM with Dynamic Write Latency
13:05-14:20 Lunch
14:20-15:40 CSA-3: Reliability and Memory Organization PA-1: Optimizing Cache Access
  Session Chair: Karthik Swaminathan, IBM Session Chair: Gang Quan, Florida International University
  1. (77) Arseniy Vitkovskiy, Paul Gratz and Vassos Soteriou. Clotho: Proactive Wearout Deceleration in Chip-Multiprocessor Interconnects 1.(207) Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita and Hiroshi Nakamura. Immediate Sleep: Reducing Energy Impact of Peripheral Circuits in STT-MRAM Caches
  2. (161) Xianwei Zhang, Youtao Zhang and Jun Yang. DLB: Dynamic Lane Borrowing for Improving Bandwidth and Performance in Hybrid Memory Cube 2. (301) Xianwei Zhang, Lei Zhao, Youtao Zhang and Jun Yang. Exploit Common Source-Line to Construct Energy Efficient Domain Wall Memory based Caches
  3. (131) Yanan Cao, Long Chen and Zhao Zhang. Memory Design for Selective Error Protection 3. (281)  Bhargavraj Patel, Gokhan Memik and Nikos Hardavellas. SCP: Synergistic Cache Compression and Prefetching
  4. (178) Si Wu, Yinlong Xu, Yongkun Li and Yunfeng Zhu. POS: A Popularity-based Online Scaling Scheme for RAID-Structured Storage Systems 4. (300) Parth Lathigara, Shankar Balachandran and Virendra Singh. Application Behavior Aware Re-reference Interval Prediction for Shared LLC
15:10~15:30 Break
15:30~16:30 LCD - 1: Application Oriented Design Special Session 1: Data Mining for Computer Design 
  Session Chair:  Jie Gu, Northwestern University Session Chair: Antonio Miele, Politecnico di Milano, Italy
  1. (241) Chaohui Du, Guoqiang Bai and Xingjun Wu. High-Speed Polynomial Multiplication Architecture for Ring-LWE Based Cryptosystems 1. "Applied Statistical Inference for System Design and Management", Benjamin Lee, Duke University
  2. (68) Guoqiang Bai, Zhenwei Zhao and Gang Chen. A High-performance Dual-field Elliptic Curve Cryptographic Processor Based on a Systolic Array 2. "Exploiting GPU architectures for dynamic invariant mining", Graziano Pravadelli, University of Verona
  3. (192) Umer Cheema, Gregory Nash, Rashid Ansari and Ashfaq Khokhar. InvArch: A Hardware-Efficient Architecture for Matrix Inversion 3. "ItHELPS: Iterative High-accuracy Error Localization in Post-Silicon", Valeria Bertacco, University of Michigan
  Tuesday, October 20th
08:00-08:30 Breakfast
08:30-09:25 Keynote
09:30-10:30 CSA-4:  Heterogeneous Computing Systems Special Session 2: Cyber-physical Integration and Design Automation for Microfluidic Biochips 
  Session Chair: Houman Homayoun, George Mason University Session Chair: Jiang Hu, Texas A&M University
  1. (88) Gabriele Pallotta, Gianluca Durelli, Antonio Miele, Cristiana Bolchini and Marco Domenico Santambrogio. An orchestrated approach to efficiently manage resources in heterogeneous system architectures 1. "Wet Computers: The Need for Design Automation and Programmability in Microfluidics", William Grover, University of California at Riverside
  2. (125) Alok Prakash, Siqi Wang, Alexandru Eugen Irimiea and Tulika Mitra. Energy-Efficient Execution of Data-Parallel Applications on Heterogeneous Mobile Platforms 2. "Cyber-physical Adaptation in Digital Microfluidic Biochips", Krishnendu Chakrabarty, Duke University
  3. (152) Jude Angelo Ambrose, Jorgen Peddersen, Yusuke Yachide, Kapil Batra and Sri Parameswaran. Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications 3. "Physical Design for Cyber-physical Microfluidic Biochips: Co-Optimization and Co-Scheduling of Biochemical Operations and On-Chip Sensors", Tsung-Yi Ho, National Tsinghua University
10:30-10:50 Break
10:50-12:30 EDA -2: Logic and Layout Synthesis TVS-2: Security 
  Session Chair: Kyle Rupnow, Advanced Digital Sciences Center, Singapore Session Chair: Simha Sethumadhavan,  Columbia University
  1. (333) Felipe Marranghello, Vinicius Callegaro, Andre Reis and Renato Ribas. SOP Based Logic Synthesis for Memristive IMPLY Stateful Logic 1. (396) Vinayaka Jyothi, Sateesh K. Addepalli and Ramesh Karri. Deep Packet Field Extraction Engine (DPFEE): A Pre-processor for Network Intrusion Detection and Denial-of-Service Detection Systems
  2. (292) Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan and Deming Chen. CSL: Coordinated and Scalable Logic Synthesis Techniques for Effective NBTI Reduction 2. (205) Chongxi Bao and Ankur Srivastava. 3D Integration: New Opportunities in Defense Against Cache-timing Side-channel Attacks
  3. (104) Chia-Yu Wu, Helmut Graeb and Jiang Hu. An Efficient ILP Approach to Analog Integrated Circuit Routing 3. (128) Chao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee and David Kaeli. Side-Channel Power Analysis of a GPU AES Implementation
  4. (59) Pietro Fezzardi, Michele Castellana and Fabrizio Ferrandi. Trace-Based Automated Logical Debugging for High-Level Synthesis Generated Circuits 4. (138) Bicky Shakya, Ujjwal Guin, Mark Tehranipoor and Domenic Forte. Performance Optimization for On-Chip Sensors to Detect Recycled Ics
  5. (234)  Jinwook Jung, Daijoon Hyun and Youngsoo Shin. Physical Synthesis of DNA Circuits with Spatially Localized Gates 5. (231) Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger and Debdeep Mukhopadhyay. From Theory to Practice of Private Circuit: A Cautionary Note
12:30-13:50 Lunch
13:50-15:30 PA-2: Optimization for Power and Speed LCD-2: Resistive Memories
  Session Chair: Nikos Hardavellas, Northwestern Universiy Session Chair: Sankar Basu, NSF
  1. (27) Hamid Reza Ghasemi, Ulya R. Karpuzcu and Nam Sung Kim. Quo Vadis: big.LITTLE or Wide DVFS Range Processors? 1. (54)  Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui and Koen Bertels. Fast Boolean Logic Mapped on Memristor Crossbar
  2. (58) Xia Zhao, Sheng Ma, Chen Li, Lu Wang and Zhiying Wang. A Low-Cost and Low-Latency Heterogeneous Ring-Chain Network for GPGPUs 2. (405) Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael Niemier and X. Sharon Hu. Reliable and High Performance STT-MRAM Architectures based on Controllable-Polarity Devices
  3. (129) Mahanama Wickramasinghe and Hui Guo. Effective Hardware-Level Thread Synchronization for High Performance and Power Efficiency in Application Specific Multithreaded Embedded Processors 3. (311)  John Demme, Steven Nowick, Bipin Rajendran and Simha Sethumadhavan. Increasing Reconfigurability with Memristive Interconnects
  4.(185) Wei Zhang, Hang Zhang and John Lach. Dynamic Core Scaling: Trading off Performance and Energy Beyond DVFS 4. (344) Manqing Mao, Yu Cao, Shimeng Yu and Chaitali Chakrabarti. OPTIMIZING LATENCY, ENERGY, AND RELIABILITY OF 1T1R RERAM THROUGH APPROPRIATE VOLTAGE SETTINGS
  5. (171) Sudarshan Srinivasan, Israel Koren and Sandip Kundu. Online Mechanism for Reliability and Power-Efficiency Management of a Dynamically Reconfigurable Core 5. (153)  Fernando García-Redondo, Marisa Lopez-Vallejo and Pablo Ituero. A Thermal Adaptive Scheme for Reliable Write Operation on RRAM Based Architectures
15:30-16:30 Poster Session
  Power Management of Pulsed-Index Communication Protocols
  Big Data on Low Power Cores Are Low Power Embedded Processors a good fit for the Big Data Workloads?
  Energy-Optimal Voltage Model Supporting a Wide Range of Nodal Switching Rates for Early Design-Space Exploration
  On the Conditions and Construction of k-Fault Tolerant Systems
  Exploring the Viability of Stochastic Computing
  A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits
  Energy-Efficient Data Movement with Sparse Transition Encoding
  A Low Power Buffer-Aided Vector Register File for LTE Baseband Signal Processing
  An Aging-Aware Battery Charge Scheme for Mobile Devices Exploiting Plug-in Time Patterns
  Analytic Processor Model for Fast Design-Space Exploration
  A Pair Selection Algorithm for Robust RO-PUF Against Environmental Variations and Aging
  Chameleon: Adaptive Energy-Efficient Heterogeneous Network-on-Chip
  2Locality-Fitting Hybrid Caches: Coupling Application-Specific Locality Characteristics with Emerging Memory Technologies for Low-Latency Low-Power Last Level Caches
  Combative Cache Efficacy Techniques: Analysis of cache replacement in the context of independent prefetching in last level cache
  An Efficient Racetrack Memory for L2 cache in GPGPUs
  ROST-C: Reliability driven Optimisation and Synthesis Techniques for Combinational Circuits
  DDAANN: Data-Driven logic synthesizer for Acceleration of forward propagation in Artificial Neural Networks
  Fixed-Function Hardware Sorting Accelerators for Near Data MapReduce Execution
  Energy-Efficient Reconstruction of Compressively Sensed Bioelectrical Signals with Stochastic Computing Circuits
  Exploiting Request Characteristics and Internal Parallelism to Improve SSD Performance
  FDRAM: DRAM Architecture Flexible in Successive Row and Column Accesses
  Runtime Multi-Optimizations for Energy Efficient On-chip Interconnections
  A Hardware-based Multi-objective Thread Mapper for Tiled Manycore Architectures
  Automatic identification of assertions and invariants with small numbers of test vectors
  A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses
  M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors
  Acceleration of Microwave Imaging Algorithms for Breast Cancer Detection via High-Level Synthesis
  Power and Performance Characterization, Analysis and Tuning for Energy-efficient Edge Detection on Atom and ARM based Platforms
  Can Assay Outcomes of Digital Microfluidic Biochips be Manipulated?  
  Hardware Support for Production Run Diagnosis of Performance Bugs
16:30-21:30 Social Event
  Wednesday, October 21st 
08:00-08:30 Breakfast
08:30-10:10 LCD-3: DDesign of Special Function Circuits PA-3: Architecting Processors Using New Circuit Technologies and Topologies
  Session Chair:  Bo Yuan, City College NY Session Chair: Shinobu Miwa, The University of Electro-Communications
  1. (136) Dawei Li, Siddhartha Joshi, Seda Ogrenci-Memik, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen and Nhan Tran. A Methodology for Power Characterization of Associative Memories 1. (90) Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alex Shapiro, Engin Ipek and Eby Friedman. Architecting a MOS Current Mode Logic (MCML) Processor for Fast, Low Noise and Energy-Efficient Computing in the Near-Threshold Regime
  2. (233) Pasquale Corsonello, Stefania Perri and Fabio Frustaci. Exploring Well Configurations for Voltage Level Converter Design in 28nm UTBB FDSOI technology 2. (347) Pierce I-Jen Chuang, Manoj Sachdev and Vincent Gaudet. VLSI Implementation of High-Throughput, Low-Energy, Configurable MIMO Detector
  3. (74)  Leo Filippini, Emre Salman and Baris Taskin. A Wirelessly Powered System with Charge Recovery Logic 3. (14) Walid J. Ghandour and Nadine J. Ghandour. A Novel Approach to Control Reconvergence Prediction
  4. (211)  Jordi Cortadella, Luciano Lavagno, Pedro López, Marc Lupon, Alberto Moreno, Antoni Roca and Sachin S. Sapatnekar. Reactive Clocks with Variability-Tracking Jitter 4. (254) Alen Bardizbanyan and Per Larsson-Edefors. Exploring Early & Late ALUs for Single-Issue In-Order Pipelines
  5. (193) Jakob Lechner and Andreas Steininger. Methods for Analysing and Improving the Fault Resilience of Delay-Insensitive Codes 5. (64)  Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian and Yoocharn Jeon. Improving Memristor Memory with Sneak Current Sharing
10:10-10:30 Break
10:30-12:10 CSA-5: Managing Multi-Core Systems TVS-3: Test Optimization
  Session Chair: Ann Gordon-Ross, University of Florida Session Chair: Adit Singh, Auburn University
  1. (191) Sudhanshu Shukla and Mainak Chaudhuri. Pool Directory: Efficient Coherence Tracking with Dynamic Directory Allocation in Many-core Systems 1. (217)  Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang and Huiyun Li. A Novel TSV Probing Technique with Adhesive Test Interposer
  2. (156) Chih-Hsun Chou and Laxmi Bhuyan. A Multicore Vacation Scheme for Thermal-Aware Packet Processing 2. (105) Jomu George Mani Paret and Otmane Ait Mohamed. A Methodology To Generate Evenly Distributed Input Stimuli By Clustering Of Variable Domain
  3. (266) Anil Kanduri, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Axel Jantsch, Pasi Liljeberg and Hannu Tenhunen. Dark Silicon Aware Runtime Mapping for Many-core Systems: A Patterning Approach 3. (160) Huajun Chen, Zichu Qi, Lin Wang and Chao Xu. A Scan Chain Optimization Method for Diagnosis
  4. (102) Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis and Houman Homayoun. Realizing Cost-Effective On-Chip Power Delivery for Many-Core Platforms by Exploiting Optimized Mapping and Power Conversion Efficiency 4. (195) Cheng Xue and R. D. Shawn Blanton. A One-Pass Test-Selection Method for Maximizing Test Coverage
  5. (390) Gustavo A. Chaparro-Baquero, Soamar Homsi, Omara Vichot, Shaolei Ren, Gang Quan and Shangping Ren. Cache Allocation for Fixed-Priority Real-Time Scheduling on Multi-Core Platforms 5. (322) Ahish Mysore Somashekar, Spyros Tragoudas and Rathish Jayabharathi. Non-Enumerative Correlation-Aware Path Selection
12:10-13:30 Lunch
13:30-15:10 CSA-6: Performance Monitoring and Characterization EDA-3: Improving Computational Efficiency of Circuit Analysis WIE Special Session
  Session Chair: Sisu Xi, Two Sigma Securities  Session Chair: Tsung-Yi Ho, National Cheng Kung University, Taiwan
  1. (196) Su Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen and Sri Parameswaran. RAPITIMATE: Rapid Performance Estimation of Pipelined Processing Systems Containing Shared Memory 1. (208) Reza Mirosanlou, Mohammadkazem Taram, Zahra Shirmohammadi and Seyed-Ghassem Miremadi. 3DCAM: A Low Overhead Crosstalk Avoidance Mechanism for TSV-Based 3D Ics
  2. (343) Rizwana Begum and Mark Hempstead. Power Agility Metrics: Measuring Dynamic Characteristics of Energy Proportionality 2. (93) Yiren Shen and Jiang Hu. GPU Acceleration for PCA-Based Statistical Static Timing Analysis
  3. (30) Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman Unsal and Adrian Cristal Kestelman. VPM: Virtual Power Meter Tool for Low-Power Many-Core/Heterogeneous Data Center Prototype 3. (284)  Vinicius Callegaro, Felipe Marranghello, Mayler Martins, Renato Ribas and Andre Reis. Bottom-up disjoint-support decomposition based on cofactor and Boolean difference analysis
  4. (81) Xianwei Zhang, Youtao Zhang and Jun Yang. TriState-SET: Proactive SET for Improved Performance of MLC Phase Change Memories 4. (265) Xiaowei Liu, Alex Doboli and Fan Ye. Optimized Local Control Strategy for Voice-based Interaction-tracking Badges for Social Applications
  5. (85) Jie Zhang, Gieseo Park, David Donofrio, Mustafa Shihab, John Shalf and Myoungsoo Jung. OpenNVM: An Open-Sourced FPGA-based NVM Controller for Low Level Memory Characterization 5. (71)  Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli. FPGA-SPICE: A Simulation-based Power Estimation Framework for FPGAs
15:10-15:30 Break
15:30-16:30 CSA-7: Application-Specific Computation Special Session 3: Reliable and Secure Mobile Cognition 
  Session Chair: Jiang Li, Shanghai Jiao Tong University Session Chair: Karthik Swaminathan, IBM T. J. Watson
  1. (375) Andrew Targhetta, Donald Owen, Francis Israel and Paul Gratz. Energy-Efficient Implementations of GF(p) and GF(2^m) Elliptic Curve Cryptography 1."Resilient Mobile Cognition: Algorithms,Innovations, and Architectures", Sharathchandra Pankanti, IBM T. J. Watson
  2. (200) Chang Song, Lei Ju and Zhiping Jia. Hybrid Sratchpad and Cache Memory Management for Energy-Efficient Parallel HEVC Encoding 2. "A Testing Platform for On-drone Computation", Dhruv Nair, IBM T. J. Watson
  3. (202) Garo Bournoutian and Alex Orailoglu. Mobile Ecosystem Driven Application-Specific Low-Power Control Microarchitecture 3. "Resilient, UAV-Embedded Real-Time Computing", Augusto J. Vega, IBM T. J. Watson