ICCD 2018


    Important Dates:

    Abstract Submission
    4-June-2018

    Paper Submission
    4-June-2018; Noon EST (Hard Deadline)

    Notification
    6-Aug-2018

    Camera-Ready
    31-Aug-2018

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2018 IEEE International Conference on Computer Design (ICCD)

Special Panel 2: Microarchitecture Side Channels: Implications for Computer Design

Panel Speakers


David Kaeli, Northeastern University        


Milos Prvulovic, Georgia Institute of Technology       


Guru Venkataramani, George Washington University       


Yinqian Zhang, The Ohio State University        

Talk 1: Microarchitecture-level Side Channels: Why Do They Occur and Ways to Prevent Them

Speaker: David Kaeli

Abstract

The computer architecture community has spent the past 50+ years designing microarchitecture-based features that improve the performance and/or efficiency of program execution. There have been a wide range of features proposed that can improve the handling of control flow and data flow in the processor. Recently, there have been a number of high-profile microarchitecture-level side-channels demonstrated on commercial CPUs and GPUs. We will highlight a few of them, and then suggests ways to avoid these problems in the future.

Bio

David Kaeli received his BS and PhD in Electrical Engineering from Rutgers University, and an MS in Computer Engineering from Syracuse University. He is presently a COE Distinguished Full Processor on the ECE faculty at Northeastern University, Boston, MA, where he directs the Northeastern University Computer Architecture Research Laboratory (NUCAR). Prior to joining Northeastern in 1993, Kaeli spent 12 years at IBM. Dr. Kaeli has published over 300 critically reviewed publications, 7 books, and 13 patents. His research spans a range of areas including microarchitecture to back-end compilers and big data applications. His current research topics include graphics processors, hardware/software security, virtualization, heterogeneous computing and multi-layer reliability. Dr. Kaeli is an IEEE Fellow and an ACM Distinguished Scientist.

Talk 2: Side-Channel Resilient Design by Planning for (Repeated) Failures

Speaker: Milos Prvulovic

Abstract

While architectural side channel vulnerabilities have garnered a lot of recent attention, most of the building blocks for these vulnerabilities have been known for a while and yet not much was done to address them. One reason for this is the focus on the attack as-demonstrated, rather than finding solutions that deny the attack’s various building blocks to future attackers. Thus almost every demonstrated attack has resulted in either “whew, we dodged this one”, “fix your program code”, or point solutions. And each time other attacks that reuse many of the prior building blocks came back.
I propose a different approach, where we enumerate the known and probably building blocks for future attacks, and build the building-block-denial capabilities in the architecture so that it can be adapted to the new reality once future attacks (inevitable) arrive. This would allow us to not pay the performance cost up-front for attacks that do not materialize, while also allowing us to have a set of well-engineered solutions for those that do materialize.

Bio

Milos Prvulovic is a Professor and Associate School Chair in the School of Computer Science at Georgia Tech. His research focuses on hardware and software support for program monitoring, debugging, and security. His research on understanding the relationship between program execution and the resulting "side-channel" signals is has been funded by DARPA, NSF, OFOSR, and ONR, and has led to numerous publications in top-tier venues, and has also garnered widespread interest from professional societies and the media. Dr. Prvulovic is a senior member of Association of Computing Machinery (ACM) and Institute of Electrical and Electronics Engineers (IEEE), and has served as the chair of the IEEE Technical Committee on Microprogramming and Microarchitecture in 2016.

Talk 3: Do Side Channels decelerate performance ramp in computing?

Speaker: Guru Venkataramani

Abstract

Information leakage has become a major issue confronting computer users, that can manifest in several forms and target varied computing resources. Among its various forms, timing channels are especially notorious for leaking secrets without leaving behind any physical evidence of an illegitimate information transfer having taken place in the system. Recently, several researchers have shown the vulnerability of mainstream processor hardware to timing channels, and highlight the need for improved architecture designs that guard themselves against such information leakage channels.
In this talk, we will discuss the vulnerabilities exposed by performance enhancing hardware to side and covert channels, and explore whether their proliferation will hinder the performance growth trends in processors. We will then deliberate on how to overcome the challenges posed by side channels through designing integrated and robust mitigation techniques spanning multiple layers of the computing stack.

Bio

Dr. Guru Prasadh Venkataramani is currently an Associate Professor of Electrical and Computer Engineering at George Washington University in Washington, DC. He received his PhD from Georgia Institute of Technology. His research area is computer architecture and security, where he has published several articles in flagship conferences and journals. Dr. Venkataramani is a recipient of NSF CAREER award in 2012, and has also won several other awards including ORAU Ralph E. Powe Junior Faculty Enhancement Award in 2010, Best poster award in IEEE/ACM PACT 2011, GWU’s Hegarty Award for Faculty Innovation in 2017. Dr. Venkataramani will be serving as one of the two General Chairs for IEEE International Symposium on High Performance Computer Architecture (HPCA) to be held in 2019 at Washington, DC. He is an elected senior member of IEEE and ACM.

Talk 4: Software Solutions to Micro-architectural Side Channels

Speaker: Yinqian Zhang

Abstract

In this talk, I will share our experience of developing software solutions to micro-architectural side channels. Micro-architectural side channels are rooted in the design of computer micro-architectures, but they often require defenses from the software layer. It is not only because hardware upgrades take time, but some side channels cannot be eradicated easily from the hardware layers. I will describe the technical challenges we have faced in our design of software solutions to side channels, especially in the context of cloud computing and SGX enclaves. I will highlight some of solutions we have devised and also the limitations to be addressed in the future. The goal of the talk is to call for closer collaboration between system and architecture researchers for the co-design of hardware/software solutions to micro-architectural side channels.

Bio

Dr. Yinqian Zhang is an assistant professor of the Department of Computer Science and Engineering at The Ohio State University. His research interest lies in computer system security. His current research focus is side-channel attacks and defenses, in the context of cloud computing and Intel SGX. He has published over 20 research papers on the topic of side channels over the past few years. Dr. Zhang is a recipient of the NSF CAREER Award (2018). He holds three U.S. patents that were derived from his previous research. In the recent years, he has served on the technical program committees of multiple security conferences, including IEEE S&P, ACM CCS, Usenix Security, and NDSS.