ICCD 2018


    Important Dates:

    Abstract Submission
    4-June-2018

    Paper Submission
    4-June-2018; Noon EST (Hard Deadline)

    Notification
    6-Aug-2018

    Camera-Ready
    31-Aug-2018

    Contact Us

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2018 IEEE International Conference on Computer Design (ICCD)


ICCD 2018: Tutorial Sessions

Note: The tutorials are open to all registered conference attendees at no additional cost.

Tutorial 1: Architectural Simulators and Boolean Satisfiability Solvers

Organizer:

  • Daniel Limbrick, North Carolina A&T State University, USA

Abstract

Integrated circuits in nanometer technologies have become more vulnerable to faults and errors, such as those induced by ionizing radiation (e.g., alpha particles, terrestrial neutrons, muons, protons, and heavy ions). Computer architects require knowledge of the application that will run on the system as well as the physical hardware that implements the system to determine: (1) where the fault occurs and (2) when the fault matters. This tutorial demonstrates tools that facilitate fault analysis and characterization on microelectronic systems across multiple levels of the abstraction stack, but in a way that specifically connects to the architecture. In space and other harsh environments, radioactive particles passing through an integrated circuit (IC) can deposit charge, leading to errant values at sensitive nodes. Traditionally, these effects lead to single-event upsets or transients, but multiple upsets or transients have become the norm in modern bulk and are common even in finFET technologies. These trends have influenced the ways in which researchers analyze systems for reliability. While much research in resilience has been devoted towards hardware faults that cause system failure, silent data corruptions (SDCs) are gaining prominence because of the demand for accuracy in high-performance computing. Future high-performance computing systems, such as exascale computing systems, will increase the demand for understanding the impact of SDCs and strategies for resilience.

Tutorial 2: Simulation of Networks-on-Chip with Noxim

Organizer:

  • Salvatore Monteleone, University of Catania, Italy

Abstract

The role played by on-chip communication systems is becoming increasingly important as the number of cores integrated into the same chip increases. Indeed, requirements introduced in the manycore era turned communication into a bottleneck in terms of performance, making it one of the major contributors to the overall cost and energy consumption. To mitigate this problem, current manycore architectures adopt a Networks-on-Chip (NoC) as communication backbone. Usually, simulation tools represent the very first and fast approach to assess the communication capability of the NoC based on-chip communication fabric. For these reasons, in this tutorial will be presented Noxim: an open, cycle-accurate NoC simulator developed in SystemC.
The tutorial will cover different aspects: after a brief introduction to the Networks-on-Chip paradigm (and the emerging wireless solution, namely WiNoC), the main features of a NoC simulator will be depicted pointing then to Noxim reference architecture and internals (i.e., how to modify & add custom features). The tutorial will also include a hands-on session in which traditional wired, as well as wireless NoC architectures, and their assessment through Noxim will be presented.

Tutorial Chairs:

For any questions on submission, please contact the Tutorial Session Chairs (Christian Pilato and Sara Vinco).