ICCD 2018

    Important Dates:

    Abstract Submission

    Paper Submission
    4-June-2018; Noon EST (Hard Deadline)



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2018 IEEE International Conference on Computer Design (ICCD)

Technical Program

The durations are: 17+3 minutes for Regular Papers (R) and 8+2 minutes for Short Papers (S). 3 and 2 minutes are the Q&A part for the regular and short papers respectively.

Note: The tutorials are open to all registered conference attendees at no additional cost.

  Sunday, October 7, 2018
14:00-18:00 Tutorial 1: Architectural Simulators and Boolean Satisfiability Solvers Tutorial 2: Simulation of Networks-on-Chip with Noxim
Session Chair: Daniel Limbrick, North Carolina A&T State University Session Chair: Salvatore Monteleone, University of Catania
16:00-16:20 Coffee Break
18:00-20:00 Reception
  Monday, October 8, 2018
07:30-08:00 Breakfast
08:00-08:30 Opening Remarks by GC and PC
08:30-09:30 Keynote 1: Fred Chong (University of Chicago)
Keynote 1: Closing the Gap between Quantum Algorithms and Machines with Hardware-Software Co-Design
09:30-10:50 Session 1: Best Papers Session
  Session Chair: Yan Solihin
  269 (R) Bozhi Liu, Roman Lysecky and Janet Roved. Composable Template Attacks using Templates for Individual Architectural Components
  105 (R) Deok Keun Oh, Mu Jun Choi and Ju Ho Kim. Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis
  344 (R) Doowon Lee, Opeoluwa Matthews and Valeria Bertacco. Low-overhead microarchitectural patching for multicore memory subsystems
  157 (R) Xiaofeng Hou, Luoyao Hao, Chao Li, Quan Chen, Wenli Zheng and Minyi Guo. Power Grab in Aggressively Provisioned Data Centers: What is the Risk and What Can Be Done About It
10:50-11:10 Break
11:10-12:30 Session 2A: SSD Session 2B: Side Channels
  Session Chair: Hung-Wei Tseng Session Chair: Ujjwal Guin
  6 (R) Te I, Murtuza Lokhandwala, Yu-Ching Hu and Hung-Wei Tseng.Pensieve: a Machine Learning Assisted SSD Layer for Extending the Lifetime 186 (R) Elmira Karimi, Zhen Hang Jiang, Yunsi Fei, and David Kaeli. A Timing Side-Channel Attack on a Mobile GPU
  21 (R) Qiao Li, Liang Shi, Riwei Pan, Cheng Ji, Xiaoqiang Li and Chun Jason Xue. Selective Compression Scheme for Read Performance Improvement on Flash Devices 251 (R) Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Analysis of Row Hammer Attack on STTRAM
  99 (R) Fei Wu, Zuo Lu, You Zhou, Xubin He, Zhihu Tan and Changsheng Xie. OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read Performance 285 (R) David Werner, Kyle Juretus, Ioannis Savidis and Mark Hempstead. Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-rich Architectures
  138 (R) Gaoxiang Xu, Zhipeng Tan, Dan Feng, Yifeng Zhu, Xinyan Zhang and Jie Xu. Cap: Exploiting Data Correlations to Improve the Performance and Endurance of SSD RAID
12:30-14:00 Lunch and Special Panel 1: Non-Volatile Memory: Will it be Memory, Storage, or Neither?
Speakers: Michael Swift (University of Wisconsin), Bruce Jacob (University of Maryland), Xipeng Shen (NCSU)
14:00-14:10 Break (for room reconfiguration)
14:10-15:30 Session 3A: Security and Capability Session 3B: Microarchitecture
  Session Chair: Guru Venkataramani Session Chair: Sheng Wei
  108 (R) Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices 7 (R) Shinji Sakai, Taishi Suenaga, Ryota Shioya and Hideki Ando. Rearranging Random Issue Queue with High IPC and Short Delay
  198 (R) Joydeep Rakshit and Kartik Mohanram. ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories 65 (R) Mustafa Cavus, Resit Sendag and Joshua J. Yi. Array Tracking Prefetcher for Indirect Accesses
  209 (R) Wenjian He, Wei Zhang, Sanjeev Das and Yang Liu. SGXlinger: A New Side-channel Attack Vector Based on Interrupt Latency against Enclave Execution 158 (S) Ricardo Alves, Stefanos Kaxiras and David Black-Schaffer. Dynamically Disabling Way-prediction to Reduce Instruction Replay
  324 (R) Hamza Omar, Syed Kamran Haider, Ling Ren, Marten van Dijk and Omer Khan.Breaking the Oblivious-RAM Bandwidth Wall 233 (S) Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos, Shrikanth Ganapathy and John Kalamatianos. Analysis and Characterization of Ultra Low Power Branch Predictors
  35 (S) Alec Roelke, Xinfei Guo and Mircea Stan. OldSpot: A Pre-RTL Model for Fine-grained Aging and Lifetime Optimization
  210 (S) Vignyan Reddy Kothinti Naresh, Rami Sheikh, Arthur Perais, and Harold W. Cain. SPF: Selective Pipeline Flush
15:30-15:50 Break
15:50-17:30 Session 4A: Logic and Circuit Design 1 Session 4B: Design Automation
  Session Chair: Jiafeng Xie Session Chair: Deliang Fan
  68 (R) Maedeh Hemmat and Azadeh Davoodi. Power-Efficient ReRAM-Aware CNN Model Generation 191 (R) Baogang Zhang and Rickard Ewetz. Software and Hardware Techniques for Reducing the Impact of Quantization Errors in Memristor Crossbar Arrays
  111 (R) Zhengyu Chen, Hai Zhou and Jie Gu. R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing 203 (R) Behzad Boroujerdian, Hussam Amrouch, Jorg Henkel and Andreas Gerstlauer. Trading Off Temperature Guardbands via Adaptive Approximations
  118 (R) Alvaro Velasquez and Sumit Kumar Jha. 3D Crosspoint Memory as a Parallel Architecture for Computing Network Reachability 323 (R) Lorenzo Ferretti, Giovanni Ansaloni and Laura Pozzi. Lattice-Traversing Design Space Exploration for High Level Synthesis
  257 (R) Seyedhamidreza Motaman and Swaroop Ghosh. Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays
  283 (R) Chiou-Yng Lee and Jiafeng Xie. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier over GF(2^{m}) Based on Overlap-Free Karatsuba Algorithm
  Tuesday, October 9, 2018
07:50-08:20 Breakfast
08:20-09:20 Keynote 2: Lin Zhong, Rice University
Keynote 2: Fixing the broken synergy at the hardware/software boundary
09:20-09:30 Break
09:30-10:50 Session 5A: Novel Architectures Session 5B: Memory 1
  Session Chair: David Kaeli Session Chair: Vignyan Kothinti Naresh
  177 (R) Jinhang Choi, Jack Sampson and Vijaykrishnan Narayanan. Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems 141 (R) Yongbin Gu and Lizhong Chen. CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs
  184 (R) Yue Xu, Hyung Gyu Lee, Xianzhang Chen, Bo Peng, Duo Liu and Liang Liang. Puppet: Energy Efficient Task Mapping For Storage-less and Converter-less Solar-Powered Non-volatile Sensor Nodes 36 (R) Jian Zhou and Jun Wang. ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory Applications
  275 (R) Kyuin Lee, Vijay Raghunathan, Anand Raghunathan and Younghyun Kim. SyncVibe: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones 234 (R) Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He and Deliang Fan. PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks
  351 (S) Joel Mandebi Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo and Christophe Bobda. FPGA Virtualization in Cloud-based Infrastructures over Virtio 86 (S) Shuo Li, Zhiguang Chen, Nong Xiao and Guangyu Sun. Path Prefetching: Accelerating Index Searches for In-Memory Databases
  77 (S) Haixin Huang, Kaixin Huang, Litong You and Linpeng Huang. Forca: Fast and Atomic Remote Direct Access to Persistent Memory 263 (S) Hao Wen and Wei Zhang. Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture
10:50-11:10 Break
11:10-12:30 Session 6A: Memory 2 Session 6B: Logic and Circuit Design 2
  Session Chair: Lizhong Chen Session Chair: Ozcan Ozturk
  2 (R) Jeremie Kim, Minesh Patel, Hasan Hassan and Onur Mutlu. Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines 15 (R) Andrew Douglass and Sunil Khatri. Synchronization of Ring-based Resonant Standing Wave Oscillators for 3D Clocking Applications
  10 (R) Andreas Kurth, Pirmin Vogel, Andrea Marongiu and Luca Benini. Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine 28 (R) Hye-Yeon Yoon and Tae-Hwan Kim. Generalized Tree Architecture for Efficient Successive-Cancellation Polar Decoding
  48 (R) Yuhai Cao, Chao Li, Quan Chen, Jingwen Leng, Minyi Guo, Jing Wang and Weigong Zhang. DR DRAM: Accelerating Memory-Read-Intensive Applications 182 (R) Rohit Chaurasiya, John Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant and Rainer Leupers. Parameterized Posit Arithmetic Hardware Generator
  19 (R) Jee Ho Ryoo, Shuang Song and Lizy John. Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme 120 (S) Soheil Salehi and Ronald F. DeMara. BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications
  . . 202 (S) Siyuan Xu and Benjamin Carrion Schafer. Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles
12:30-14:00 Lunch and Special Panel 2: Microarchitecture Side Channels: Implications for Computer Design
Speakers: David Kaeli (Northeastern University), Milos Prvulovic (Georgia Institute of Technology), Guru Venkataramani (George Washington University), Yinqian Zhang (The Ohio State University)
14:00-14:10 Break (for room reconfiguration)
14:10-15:30 Session 7A: Accelerators and GPUs Session 7B: Potpouri 1
  Session Chair: Xipeng Shen Session Chair: Lin Zhong
  97 (R) Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting and Andreas Koch. Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-based Accelerators 346 (R) Fei Wu, Yue Zhu, Qin Xiong, Zhonghai Lu, You Zhou, Weizhen Kong and Changsheng Xie. Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications
  142 (R) Kyu Yeun Kim and Woongki Baek. BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement 248 (R) Kunal Bharathi, Harsh Kumar, Abbas Fairouz, Ahmad Al Kawam and Sunil P. Khatri. A Plain-text Incremental Compression (PIC) Technique with Fast Lookup Ability
  175 (R) Jan Kucera, Lukas Kekely, Adam Piecek and Jan Korenek. General IDS Acceleration for High-Speed Networks 1 (R) Huixiang Chen, Yuting Dai, Rui Xue, Kan Zhong and Tao Li. Towards Efficient Micoarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality Era
  259 (R) Siavash Rezaei, Kanghee Kim and Eli Bozorgzadeh. Scalable Multi-Queue Data Transfer Scheme for FPGA-based Multi-Accelerators 163 (S) Sujeong Jo, Hanmin Park, Gunhee Lee and Kiyoung Choi. Training Neural Networks with Low Precision Dynamic Fixed-Point
  95 (S) Zhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng and Jiang Xu. Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing
15:30 - 15:50 Break
15:50-17:10 Session 8A: NVM Session 8B: Test and Verification
  Session Chair: Milos Prvulovic Session Chair: Miroslav Velev
  8 (R) Amirsaman Memaripour and Steven Swanson. Breeze: User-Level Access to Non-Volatile Main Memories for Legacy Software 117 (R) Tania Khanna and Michael Hsiao. Guiding RTL Test Generation Using Relevant Potential Invariants
  16 (R) Payman Behnam, Arjun Chowdhury and Mahdi Nazm Bojnordi. R-Cache: A Highly Set-Associative In-Package Cache using Memristive Arrays 224 (R) Zeye Liu and Ronald Blanton. Back-End Layout Reflection for Test Chip Design
  96 (R) Fan Yang, Junbin Kang, Shuai Ma and Jinpeng Huai. A Highly Non-Volatile Memory Scalable and Efficient File System 247 (R) Abdullah Ash-Saki and Swaroop Ghosh. How multi-threshold designs can protect analog IPs?
  197 (R) Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang and Radu Teodorescu. NVCool: When Non-Volatile Caches Meet Cold Boot Attacks 42 (S) Kunal Bansal and Michael Hsiao. Optimization of Mutant Space for RTL Test Generation
  . . 196 (S) Mohamed Ayoub Neggaz, Ihsen Alouani, Pablo Ribalta and Smail Niar. A reliability study on CNNs for critical embedded systems
16:45 - 18:30 Break
18:30 - 20:30 Banquet
  Wednesday, October 10, 2018
08:00-08:30 Breakfast
09:00-10:20 Session 9A: Network on Chip and Synchronization Session 9B: Potpouri 2
  Session Chair: Amro Awad Session Chair: Miroslav Velev
  115 (R) Yuechen Chen, Md Farhadur Reza and Ahmed Louri. DEC-NoC: An Approximate Framework based on Dynamic Error Control with Applications to Energy-efficient NoCs 13 (R) Bikash Poudel and Arslan Munir. Design and Evaluation of a PVT Variation-Resistant TRNG Circuit
  207 (R) Padmaja Bhamidipati and Avinash Kodi. RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture 348 (R) Nadir Carreon, Sixing Lu and Roman Lysecky. Hardware-based Probabilistic Threat Detection and Estimation for Embedded Systems
  325 (R) Halit Dogan, Masab Ahmad, Jose Joao and Omer Khan. Accelerating Synchronization in Graph Analytics using Moving Compute to Data Model on Tilera TILE-Gx72 355 (R) Suyuan Chen and Ranga Vemuri. Reverse Engineering of Split Manufactured Sequential Circuits using Satisfiability Checking
  62 (S) Cunlu Li, Dezun Dong and Xiangke Liao. Eca-Router : On Achieving Endpoint Congestion Aware Switch Allocation in the On-Chip Network 334 (R) Yingyi Luo, Xiaoyang Wang, Seda Ogrenci-Memik, Gokhan Memik, Kazutomo Yoshii and Pete Beckman. Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes
  219 (S) Dara Rahmati, Sobhan Masoudi, Ahmad Khonsari and Reza Sabbaghi. Accurate Performance Bounds Calculation for Dynamic Voltage-Frequency Islands in Best Effort Networks-on-Chip
10:20-10:40 Break
10:40-12:00 Session 10A: File System and Cloud Session 10B: FPGA and Machine Learning
  Session Chair: Amro Awad Session Chair: Miroslav Velev
  362 (R) Qian Zhang, Yongbin Zhou, Shuang Qiu, Wei Cheng, Jingdian Ming and Rui Zhang. A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks 165 (R) Minghua Shen and Nong Xiao. Fine-Grained Parallel Routing for FPGAs with Selective Expansion
  104 (R) Chunxue Zuo, Fang Wang, Ping Huang, Yuchong Hu, Dan Feng and Yucheng Zhang. PFCG: Improving the Restore Performance of Package Datasets in Deduplication Systems 188 (R) Siyuan Xu and Benjamin Carrion Schafer. DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures
  54 (S) Yanwen Xie, Dan Feng, Fang Wang, Xinyan Zhang, Jizhong Han and Xuehai Tang. OME: An Optimized Modeling Engine for Disk Failure Prediction in Heterogeneous Datacenter 338 (R) Minghua Shen and Nong Xiao. Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAs
  89 (S) Chuanwen Wang, Diansen Sun, Yunpeng Chai and Fang Zhou. Enabling Accurate Performance Isolation on Hybrid Storage Devices in Cloud Environment 252 (R) Andrew B. Kahng, Uday Mallappa and Lawrence Saul. Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis
  139 (S) Ke Zhou, Yu Zhang, Ping Huang, Hua Wang, Yongguang Ji, Bin Cheng and Ying Liu. LEA: A Lazy Eviction Algorithm for SSD Cache in Cloud Block Storage
  14 (S) Jianmin Qian, Jian Li, Ruhui Ma and Haibing Guan. Optimizing Virtual Resource Management for Consolidated NUMA Systems
12:00-12:15 Closing