ICCD 2017


    Important Dates:

    Abstract Submission
    Closed on 19-Jun-2017

    Paper Submission
    Closed on 28-Jun-2017

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    Closed on 31-Aug-2017

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    30-Sep-2017

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2017 IEEE International Conference on Computer Design (ICCD)


Tentative Program

The durations are: 15+3 minutes for Regular Papers (R) and 6+2 minutes for Short Papers (S). 3 and 2 minutes are the Q&A part for the regular and short papers respectively.

  Sunday. November 5, 2017
Tutorial 1 (15:00-17:45) : Harnessing Data Science for the HW Verification Process Tutorial 2 (15:00-20:00) : Cloud-FPGA Programming with AWS F1, SDAccel and the CAOS Framework
Session Chairs: Raviv Gal and Avi Ziv Session Chairs: Lorenzo Di Tucci, Marco Rabozzi, and Marco Domenico Santambrogio, Parimal Patel
16:30-16:45 Coffee Break
18:00-20:00 Reception
 
  Monday. November 6, 2017
08:00-08:30 Breakfast
08:30-9:30 Opening & Keynote by Yan Solihin
9:40-11:10 Best Papers Session
  Session Chair: Ozgur Sinanoglu
  120 (R) Kashif Naveed and Hui Wu. Aster: Multi-bit Soft Error Recovery Using Idempotent Processing
  234 (R) Weiwen Jiang, Edwin H.-M. Sha, Qingfeng Zhuge, Lei Yang, Hailiang Dong and Xianzhang Chen. On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints
  177 (R) M. Hassan Najafi and David Lilja. High Quality Down-Sampling For Deterministic Approaches to Stochastic Computing
  85 (R) Mohammad Khavari Tavana, Yunsi Fei and David Kaeli. Nacre: Durable, Secure and Energy-efficient Non-Volatile Memory Utilizing Data Versioning
  5 (R) Benedikt Dietrich, Nadja Peters, Sangyoung Park and Samarjit Chakraborty. Estimating the Limits of CPU Power Management for Mobile Games
11:10-11:30 Break
11:30-13:00 1A: Hardware Security I 1B: Read-Write Optimizations for Non-Volative Memory
  Session Chair: David Kaeli Session Chair: Paul V. Gratz
  69 (R) Huili Chen, Seetal Potluri and Farinaz Koushanfar. BioChipWork: Reverse Engineering of Microfluidic Biochips 136 (R) Shengan Zheng, Hong Mei, Linpeng Huang, Yanyan Shen and Yanmin Zhu. Adaptive Prefetching for Accelerating Read and Write in NVM-based File Systems
  116 (R) Sixing Lu, Roman Lysecky and Jerzy Rozenblit. Subcomponent Timing based Detection of Malware in Embedded Systems 196 (R) Xiaoyi Zhang, Dan Feng, Yu Hua and Jianxi Chen. A Cost-efficient NVM-based Journaling Scheme for File Systems
  154 (R) Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty and Ramesh Karri. Security Trade-offs in Microfluidic Routing Fabrics 337 (R) Tianyue Lu, Yuhang Liu, Haiyang Pan and Mingyu Chen. TDV cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective
  245 (R) Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay and Swaroop Ghosh. Side-Channel Attack on STTRAM based Cache for Cryptographic Application 349 (R) Dennis Antony Varkey, Biswabandan Panda and Madhu Mutyam. RCTP: Region Correlated Temporal Prefetcher
  172 (S) Abhishek Chakraborty, Yang Xie and Ankur Srivastava. Template Attack Based Deobfuscation of Integrated Circuits 240 (R) Tianming Yang, Haitao Wu and Ping Huang. A Shingle-aware Cache Management Policy for High Performance DM SMR Devices
  221 (S) Yuntao Liu, Yang Xie and Ankur Srivastava. Neural Trojans
13:00-14:00 Lunch
14:00-15:30 2A: Stochastic, Approximate, and Unary Computing 2B: Energy-Efficiency through Heterogeneity
  Session Chair: Yanzhi Wang Session Chair: Lide Duan
  12 (R) Tongxin Yang, Tomoaki Ukezono and Toshinori Sato. Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor 310 (R) Hossein Sayadi, Nisarg Patel, Avesta Sasan and Houman Homayoun.Machine Learning-based Approaches for Energy Efficiency Prediction and Scheduling in Composite Cores Architectures
  129 (R) Bingzhe Li, Yaobin Qin, Bo Yuan and David Lilja. Neural Network Classifiers using Stochastic Computing with a Hardware-Oriented Approximate Activation Function 263 (R) Samuel Steffl and Sherief Reda. LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs
  86 (R) Joonsang Yu, Kyounghoon Kim, Jongeun Lee and Kiyoung Choi.Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks 179 (R) Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, Rhett Davis and Paul Franzon.H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor
  115 (R) Siyuan Xu and Benjamin Carrion Schafer.Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-architecture to Dynamic Workloads 327 (R) Ling Wang and Yadong Wang.ABDTR: Approximation-Based Dynamic Traffic Regulation for Networks-on-Chip Systems
  279 (S) Xiaoliang Chen, Ahmed Eltawil and Fadi Kurdahi.Low Latency Approximate Adder for Highly Correlated Input Streams 394 (S) Diman Zad Tootaghaj and Farshid Farhat.CAGE: A Contention-Aware Game-theoretic Model for Heterogenous Resource Assignment
  256 (S) M. Hassan Najafi, David Lilja, Marc Riedel and Kia Bazargan.Power and Area Efficient Sorting Networks using Unary Processing 176 (S) Suhaimi Abd Ishak, Hui Wu and Umair Ullah Tariq.Energy-Aware Task Scheduling on Heterogeneous NoC-based MPSoCs
15:30-15:50 Break
15:50-17:20 3A: Debugging and Validation 3B: Graph Processing and NoC Architectures
  Session Chair: Victor N Kravets Session Chair: Mircea Stan
  194 (R) Kamran Rahmani and Prabhat Mishra. Feature-based Signal Selection for Post-silicon Debug using Machine Learning 369 (R) Tiago Alves, Leandro A. J. Marzulo, Felipe M. G. Franca and Sandip Kundu. Concurrency Analysis in Dynamic Dataflow Graphs
  317 (R) Xiaobang Liu and Ranga Vemuri. Effective Signal Restoration in Post-Silicon Validation 315 (R) Hamza Omar, Masab Ahmad and Omer Khan. GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms
  60 (R) Yuting Cao, Hao Zheng, Hernan Palombo, Sandip Ray and Jin Yang. A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug 334 (R) Jing Chen and Xue Liu. A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function Evaluation
  268 (R) Alif Ahmed and Prabhat Mishra. QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models 142 (R) Peitian Pan and Chao Li. Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory Machines
  406 (R) Farimah Farahmandi and Prabhat Mishra. Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction 329 (S) Yuya Maruyama, Shinpei Kato and Takuya Azumi. Exploring Scalable Data Allocation and Parallel Computing on NoC-based Embedded Many Cores
  347 (S) Mourad Dridi, Stephane Rubini, Mounir Lallali, Johanna Sepulveda, Frank Singhoff and Jean-Philippe Diguet. DAS: an efficient NoC Router for Mixed-Criticality Real-Time Systems
   
  Tuesday, November 7, 2017
07:45-08:30 Breakfast
08:30-09:30 Keynote by Radha Ratnaparkhi
09:30-11:00 4A: EDA with Focus on Multicore, FPGAs and 3D 4B: Hardware Acceleration for Neural Networks
  Session Chair: Jack Tang Session Chair: Xue Lin
  231 (R) Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande and Krishnendu Chakrabarty. Monolithic 3D-enabled High-Performance and Energy Efficient Network-on-Chip 155 (R) Alireza Khodamoradi and Ryan Kastner. O(N)-Space Spatiotemporal Filters for Reducing Noise in Neuromorphic Vision Sensors
  407 (R) Yuanwen Huang and Prabhat Mishra. Vulnerability-aware Energy Optimization using Cache Reconfiguration and Partitioning in Multicore Systems 210 (R) Chi Lo, Yu-Yi Su, Chun-Yi Lee and Shih-Chieh Chang. A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing
  182 (R) Minghua Shen and Guojie Luo. Dependency-Aware Parallel Routing for Large-Scale FPGAs 237 (R) Chengning Wang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu and Yang Zhang. DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory
  29 (R) Ke Liu, Mengying Zhao, Lei Ju, Zhiping Jia, Chun Jason Xue and Jingtong Hu. Design Exploration for Multiple Level Cell based Non-volatile FPGAs 212 (R) Ruizhe Cai, Ao Ren, Luhao Wang, Massoud Pedram and Yanzhi Wang. Hardware Acceleration of Bayesian Neural Networks using RAM based Linear Feedback Gaussian Random Number Generators
  353 (S) Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin and Sorin Cotofana. LDPC-Based Adaptive Multi-Error Correction for 3D Memories 227 (S) Nick Iliev and Amit Trivedi. Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network
  405 (S) Tuck-Boon Chan, Wei-Ting Jonas Chan and Andrew B. Kahng. ILP-Based Identification of Opportunistic Redundant Logic Insertions for Opportunistic Yield Improvement During Early Process Learning 130 (S) Abbas Fairouz and Sunil P. Khatri. An FPGA-based Coprocessor for Hash Unit Acceleration
11:00-11:20 Break
11:20-12:50 5A: Hardware Security II 5B: Memory and Cache Optimizations
  Session Chair: Raviv Gal Session Chair: Madhu Mutyam
  148 (R) Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou and Jianlei Yang.Power Profile Equalizer: a Lightweight Countermeasure against Side-channel Attack 84 (R) Newton Singh, Sujit Kumar Mahto, Suhit Pai and Virendra Singh. DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching
  278 (R) Farimah Farahmandi and Prabhat Mishra. FSM Anomaly Detection using Formal Analysis 271 (R) Pai Chen, Jianhui Yue, Xiaofei Liao and Hai Jin. Simultaneously Optimizing DRAM Cache Latency and Hit Rate
  357 (R) Chenguang Wang, Yici Cai and Qiang Zhou. Automatic Security Property Generation for Detecting Information-leaking Hardware Trojans 258 (R) Akshay Lahiry and David Kaeli. Dual Dictionary Compression for the Last Level Cache
  79 (R) Ahmed Waheed Khan, Tanya Wanchoo, Gokhan Mumcu and Selcuk Ksse. Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks 8 (R) Georgios Mappouras, Alireza Vahid, Robert Calderbank, Derek Hower and Daniel Sorin. Jenga: Efficient Fault Tolerance for Stacked DRAM
  244 (S) Vinayaka Jyothi, Ashik Poojari, Richard Stern and Ramesh Karri. Fingerprinting Field Programmable Gate Arrays 90 (S) Jiajun Wang, Reena Panda and Lizy John. SelSMaP: A Selective Stride Masking Prefetching Scheme
  293 (S) Qutaiba Alasad and Jiann-Shiun Yuan. Logic Obfuscation against IC Reverse Engineering Attacks using Polymorphic Gates 285 (S) Sushant Kondguli and Michael Huang. T2: A Highly Accurate and Energy Efficient Stride Prefetcher
12:50-14:00 Lunch
14:00-15:40 6A: Verification and Fault Tolerance 6B: Lithography and Patterning.
  Session Chair: Avi Ziv Session Chair: Vinayaka Jyothi
  114 (R) Thomas Fehmel, Dominik Stoffel and Wolfgang Kunz. Generation of Abstract Driver Models for IP Integration Verification 375 (R) Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric and David Pan. DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node
  126 (R) Madiha Gul, Muhamed Chouikha and Mamadou Wade. Crosstalk Aware and Burst Error Fault Tolerance Mechanism for Reliable Communication 346 (S) Sudipta Paul, Pritha Banerjee and Susmita Sur-Kolay. Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography
  211 (R) Mehran Goli, Jannis Stoppe and Rolf Drechsler. Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata 25 (S) Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan and David Z. Pan. Patterning Aware Design Optimization of Selective Etching in N5 and Beyond
  367 (R) Kimia Soleimani, Ahmad Patooghy, Nasim Soltani, Lake Bu and Michel Kinsy. Crosstalk Free Code Generation to Protect Network on Chips Against Crosstalk Faults Special Session 1: On how to design and manage complex heterogeneous distributed computing systems.
Session Chairs: Marco Domenico Santambrogio, Marco Rabozzi, and Jose L. Ayala
  66 (S) Abhishek Das and Nur A. Touba. Limited Magnitude Error Correction using OLS Codes for Memories with Multilevel Cells 425 Michaela Blott, Thomas Preusser, Yaman Umuroglu, Miriam Leeser, Nicholas Fraser, Kenneth O'Brien and Giulio Gambardella. Scaling Neural Network Performance through Customized Hardware Architecture
  254 (S) Jiangwei Zhang, Donald Kline Jr, Liang Fang, Rami Melhem and Alex Jones. Yoda: Judge me by my size, do you? 422 Lorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo and Marco Domenico Santambrogio. The role of CAD frameworks in heterogeneous FPGA-based cloud systems
  22 (S) Sonal Pinto and Michael S. Hsiao. Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance 420 Emanuele Del Sozzo, Riyadh Baghdadi, Saman Amarasinghe and Marco Domenico Santambrogio. A Common Backend for Hardware Acceleration on FPGA
  417 Alberto Scolari, Yunseong Lee, Markus Weimer and Matteo Interlandi. Towards Accelerating Generic Machine Learning Prediction Pipelines
  418 Nils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev and Wayne Luk. Convolutional Neural Networks on Dataflow Engines
16:00 - 21:00 Social Event at the Museum of Science, Boston
   
  Wednesday, November 8, 2017
07:45-08:30 Breakfast
08:30-09:30 Keynote by Philip Emma
09:30-11:00 7A: LCD with Focus on Emerging Technology 7B: Power-Performance Optimization of Multicore Architectures
  Session Chair: Samah Saeed Session Chair: Lei Wang
  266 (R) Zhezhi He, Shaahin Angizi and Deliang Fan. Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction 105 (R) Christopher Giles and Mark Heinrich. M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU Systems
  108 (R) Julio Villalba-Moreno and Javier Hormigo Aguilar. Floating Point Square Root under HUB Format 209 (R) Sudhanshu Shukla and Mainak Chaudhuri.Sharing-aware Efficient Private Caching in Many-core Server Processors
  35 (R) Wen Wen, Youtao Zhang and Jun Yang. Read Error Resilient MLC STT-MRAM based Last Level Cache 392 (R) Lei Mo, Angeliki Kritikakou and Olivier Sentieys. Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores
  216 (R) Behzad Zeinali, Jens K. Madsen, Praveen Raghavan and Farshad Moradi. Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching 257 (R) Sabrina Neuman, Jason Miller, Daniel Sanchez and Srini Devadas. Using Application-Level Thread Progress Information to Manage Power and Performance
  313 (S) Aditya Dalakoti, Merritt Miller and Forrest Brewer. Pulse Ring Oscillator Tuning via Pulse Dynamics 96 (S) Siyuan Xu and Benjamin Carrion Schaefer. Configurable SoC In Situ Hardware/Software Co-Design Design Space Exploration
  400 (S) Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai and Yung-Fa Chou. DLL-Assisted Clock Synchronization Method for Multi-Die ICs 354 (S) David Kaeli and Navid Farazmand. Quality Of Service-aware Dynamic Voltage and Frequency Scaling for Mobile 3D Graphics Applications
11:00-11:20 Break
11:20-12:50 8A: Synthesis and Security 8B: Cloud and Storage Solutions
  Session Chair: Nektarios Tsoutsos Session Chair: Miroslav Velev
  57 (R) Lorenzo Ferretti, Giovanni Ansaloni and Laura Pozzi. Cluster-Based Heuristic for High Level Synthesis Design Space Exploration 233 (R) Wonil Choi, Myoungsoo Jung, Mahmut Kandemir and Chita Das. A Scale-Out Enterprise Storage Architecture
  343 (R) Yue Yao, Shuyang Huang, Chen Wang, Yi Wu and Weikang Qian. Approximate Disjoint Bi-decomposition and Its Application to Approximate Logic Synthesis 145 (R) Tianwei Zhang, Yuan Xu, Yungang Bao and Ruby Lee. CloudShelter: Protecting Virtual Machines’ Memory Resource Availability in Cloud Computing
  249 (R) Steven Hoover. Timing-Abstract Circuit Design in Transaction-Level Verilog 147 (R) Yazhi Feng, Dan Feng, Wei Tong, Yu Jiang and Chuanqi Liu. Using Disturbance Compensation and Data Clustering (DC)^2 to Improve Reliability and Performance of 3D MLC Flash Memory
  183 (S) Atieh Lotfi and Rajesh Gupta. ReHLS: Resource-aware Program Transformation Workflow for High-level Synthesis 401 (R) Jie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li and Wen Zhou. Improving Performance of TLC RRAM with Compression-Ratio-Aware Data Encoding
  282 (S) Samah Saeed, Nithin Mahendran, Alwin Zulehner, Ramesh Karri and Robert Wille. Can an IP/IC Pirate Identify the Synthesis Approach of a Reversible Circuit? 139 (S) Jie Xu, Dan Feng, Wei Tong, Jingning Liu and Wen Zhou. Encoding Separately: An Energy-efficient Write Scheme for MLC STT-RAM
  284 (S) Pei Luo, Liwei Zhang, Zhen Jiang, Yunsi Fei, A. Adam Ding and Thomas Wahl. A First Step Towards Automatic Compiler Assisted Threshold Implementation Design 229 (S) Mingzhe Zhang, Lunkai Zhang, Lei Jiang, Frederic Chong and Zhiyong Liu. Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes
  241 (S) Vinayaka Jyothi, Prashanth Krishnamurthy, Farshad Khorrami and Ramesh Karri. TAINT: Tool for Automated INsertion of Trojans
12:50-14:00 Lunch
14:00-15:00 Special Session 2: Effective Voltage Scaling in Late CMOS Era Special Session 3: Spin-computing: lower the barrier between memory and logic
  Session Chairs: Pradip Bose and Alper Buyuktosunoglu Session Chairs: Deliang Fan and Wang Kang
  424 Patrick Hansen, Sreela Kodali, Niamh Mulholland, Paul Whatmough, David Brooks and Gu-Yeon Wei. Applications of Deep Neural Networks for Ultra Low Power IoT 426 Yong Shim, Akhilesh Jaiswal and Kaushik Roy. Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization
  421 Eric Cheng, Jacob Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith Campbell, Deming Chen, Cheng-Yong Cher, Hyungmin Cho5, Binh Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz Szafaryn, Christos Vezyrtzis, Subhasish Mitra. Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights 423 Deliang Fan and Shaahin Angizi. Very Low Voltage (VLV) DesignEnergy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM
  416 Alec Roelke, Schuyler Eldridge, Karthik Swaminathan, Nandhini Chandramoorthy, Alper Buyuktosunoglu, Xinfei Guo, Vaibhav Verma, Rajiv Joshi, Pradip Bose, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Kevin Skadron and Mircea Stan. Pre-RTL Voltage and Power Optimization for Low-cost, Thermally Challenged Multicore Chips 419 Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang and Weisheng Zhao. Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device
  427 Pradip Bose, David Brooks, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Rajiv Joshi, Subhasish Mitra, Arun Paidimarri, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Christos Vezyrtzis, Gu-Yeon Wei and Matthew Ziegler. Very Low Voltage (VLV) Design
15:00-15:20 Break
15:20-16:50 9A: Architecture and Microarchitecture Optimizations 9B: Novel Architecture with 3D and Flash Memory
  Session Chair: Miroslav Velev Session Chair: Michel Kinsy
  140 (R) Janibul Bashir and Smruti R. Sarangi. NUPlet: A Photonics Based Multi-Chip NUCA Architecture 190 (R) Hao Liu, Linpeng Huang, Yanmin Zhu and Yanyan Shen. LibreKV: A Persistent In-Memory Key-Value Store
  275 (R) Armin Haj Aboutalebi and Lide Duan. RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory Under Read Disturbance 398 (R) Meng Zhang, Fei Wu, Yajuan Du, Chengmo Yang, Changsheng Xie and Jiguang Wan. CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash
  111 (R) Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo and Lieven Eeckhout. BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads 91 (R) Andrew Douglass and Sunil P Khatri. Fast, Ring-based Design of 3D Stacked DRAM
  95 (R) Alexandre Joannou, Jonathan Woodruff, Simon W. Moore, Robert Kovacsics, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Peter G. Neumann, Edward Napierala, John Baldwin, A. Theodore Markettos, Khilan Gudka, Alfredo Mazzinghi, Alexander Richardson, Stacey Son and Alex Bradbury. Efficient Tagged Memory 259 (R) Nektarios Georgios Tsoutsos, Oleg Mazonka and Michail Maniatakos. Memory-bounded Randomness for Hardware-constrained Encrypted Computation
  191 (S) Kramer Straube, Christopher Nitta, Rajeevan Amirtharajah, Matthew Farrens and Venkatesh Akella. Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing 88 (S) Qiao Li, Liang Shi, Yejia Di, Yajuan Du, Chun Jason Xue and Edwin H.-M. Sha. Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems
  186 (S) Chaobing Zhou, Libo Huang, Tan Zhang, Yongwen Wang, Chengyi Zhang and Qiang Dou. Effective Optimization of Branch Predictors through Lightweight Simulation 149 (S) Abhishek Koneru, Sukeshwar Kannan and Krishnendu Chakrabarty. A Design-for-Test Solution for Monolithic 3D Integrated Circuits