ICCD 2024
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Important Dates:
Abstract Submission
May 05, 2024, 11:59pm AOE
Paper Submission
May 12, 2024, 11:59pm AOE
The 42nd IEEE International Conference on Computer Design (ICCD 2024)
November, 2024
Milan, Italy
ICCD encompasses a wide range of topics in the research, design, and implementation of
computer systems and their components. ICCD's multi-disciplinary emphasis provides an
ideal environment for developers and researchers to discuss practical and theoretical
work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology.
Track 1. Computing Systems: System architecture; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic,
bio-inspired computing, machine learning and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale system, and serverless computing.
Track 2. Software Architectures, Compilers, and Tool Chains: Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design,
and co-design for embedded/real-time systems; Middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.
Track 3. Hardware Architectures: Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining,
caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware
support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.
Track 4. Test, Verification, and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods;
Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving;
Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test, security and trust.
Track 5. Electronic Design Automation: System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power,
variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains,
asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies
(photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.
Track 6. Logic and Circuit Design: Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high
performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMS, nano-spintronics, quantum, flexible
electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits.
Sponsored by:
