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ICCD 2018

    Important Dates:

    Abstract Submission

    Paper Submission
    4-June-2018; Noon EST (Hard Deadline)



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    Web Chair

Mountain View

The 36th IEEE International Conference on Computer Design 

October 7 - 10, 2018

Orlando, Florida, USA

Holiday Inn Orlando – Disney Springs® Area


Information about ICCD 2019


Web Publication Link

Keynote Speakers

Keynote 1: Professor Fred Chong (University of Chicago)

Keynote 2: Professor Lin Zhong (Rice University)

Special Panels

Panel 1: Non-Volatile Memory: Will it be Memory, Storage, or Neither?

Speakers: Michael Swift (Univ. of Wisconsin), Bruce Jacob (Univ. of Maryland), Xipeng Shen (NC State Univ.)

Panel 2: Microarchitecture Side Channels: Implications for Computer Design

Speakers: David Kaeli (Northeastern Univ.), Milos Prvulovic (Georgia Institute of Technology), Guru Venkataramani (George Washington Univ.), Yinqian Zhang (Ohio State Univ.)


The IEEE International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, verification and test, design tools and methodologies, circuit design, and technology.
We especially encourage submissions that look forward to future systems and technologies. Manuscripts describing original work on any topic from the scope of ICCD are welcome. Authors are asked to submit technical papers in accordance to the author’s instructions in one of the following five conference tracks:
Computer Systems: Systems architecture (memory hierarchy, memory, storage, NoC), and systems software (compiler, programming lan-guage/model, OS, hypervisor, runtime) design and co-design for: embedded/real-time systems, IoT devices, high-performance computing servers, data center and cloud/edge servers; General purpose multi/many cores, co-processors, accelerators, and application-specific sys-tems; Support for security, reliability, and energy efficiency and proportionality; Architecture and compiler for thread parallelism, synchronization, and communication; Virtual memory; System integration of emerging technologies: NVMs, quantum, etc.
Processor Architecture: Microarchitecture design techniques for single- and multi-core processors: instruction-level parallelism, pipelining, caching, branch prediction, multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, application-specific and digital signal processor design; Hardware support for pro-cessor virtualization; Real-life design challenges: case stud-ies, tradeoffs, postmortems.
Logic and Circuit Design: Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability and radiation; Design techniques for emerging process technol-ogies (MEMs, spintronics nano, quantum, flexible electron-ics); Asynchronous circuits; Signal processing, graphic processor and arithmetic circuits.
Electronic Design Automation: High-level, logic and physical synthesis; Physical planning, design and early estimation for large circuits; Automatic analysis and optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC methodologies; System-level design and syn-thesis; Tools and design methods for emerging technolo-gies (MEMs, spintronics, nano, quantum).
Test, Verification and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF Testing; Statistical Test Methods; Large volume yield Analysis and Learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware de-signs; Equivalence checking, property checking, and theo-rem proving; Constrained-random test generation; High-level design and SoC validation. Hardware security primi-tives; Side channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.

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