ICCD 2014 - Conference Program

Final Program

Champagne A Champagne B
8:30am - 10:00am Opening &
KEYNOTE I: Peter Hofstee, IBM
Exploring models of computation and the consequences for systems for Big Data
10:00am - 10:20m Coffee break
10:20am - 12:00pm
12:00pm - 1:20pm LUNCH
1:20pm - 3:00pm
Best paper session
3:00pm - 3:20pm
Coffee break
3:20pm - 5:00pm PA-1 Special session A
5:00pm - 6:40pm TVS Embedded tutorial
6:40pm -
9:00am - 10:00am KEYNOTE II: Joerg Henkel, KIT
Dependability of On-Chip Systems in the Dark Silicon Era
10:00am - 10:20am Coffee break
10:20am - 12:00pm
12:00pm - 1:20pm LUNCH
1:20pm - 3:00pm PA-2 Special session B
3:00pm - 3:20pm Coffee break
3:20pm - 5:00pm CSA-3 LCD-2
5:00pm - 6:30pm
Poster session
6:30pm - 9:00pm BANQUET &
KEYNOTE III: Massoud Pedram, USC
Designing Energy-Efficient Information Processing Systems
8:30am - 10:10am PA-3
10:10am - 10:30am Coffee break
10:30am - 12:10am CSA-4 EDA-2
12:10am - 12:30pm Closing


Full Program


10/20 (Mon) 10:20 – 12:00
CSA-1: Memory Architecture
Session Chair: John Kim (KAIST, Korea)

    • 3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time
      Ishan Thakkar and Sudeep Pasricha (Colorado State Univ)
    • The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost
      Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi and Onur Mutlu (Carnegie Mellon Univ)
    • Leveling to the Last Mile: Near-zero-cost Bit Level Wear Leveling for PCM based Main Memory
      Mengying Zhao and Chun Jason Xue (City Univ of Hong Kong)
      Chengmo Yang (Univ of Delaware)
    • ProactiveDRAM: A DRAM-initiated Retention Management Scheme
      Jue Wang (Pennsylvania State Univ), Xiangyu Dong (Qualcomm) and Yuan Xie (Pennsylvania State Univ)
    • HAP: Hybrid-memory-Aware Partition in Shared Last-Level Cache
      Wei Wei, Dejun Jiang, Jin Xiong and Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences)
    • REEM: Failure/Non-Failure region Estimation method for SRAM yield analysis
      Manish Rana and Ramon Canal (Universitat Politecnica De Catalunya)
    • Efficient Design of FIR Filters Using Hybrid Multiple Constant Multiplications on FPGA
      Levent Aksoy, Paulo Flores and Jose Monteiro (INESC-ID)
    • A Low Power Accuracy Configurable Floating Point Multiplier
      Hang Zhang, Wei Zhang and John Lach (Univ of Virginia)
    • An Area-efficient Ternary CAM Design using Floating Gate Transistors
      Viacheslav Fedorov, Monther Abusultan and Sunil Khatri (Texas A&M Univ)
    • Exploring the State Dependent SET Sensitivity of Asynchronous Logic – The Muller-Pipeline Example
      Andreas Steininger (Vienna Univ of Technology), Dan Alexandrescu (IROC Technology), Varadan Savulimedu Veeravalli (Vienna Univ of Technology) and Lorena Anghel (Laboratoire TIMA)


10/20 (Mon) 13:20 – 15:00
Best Paper Session
Session Chair: Sule Ozev (Arizona State Univ, USA)

    • iRMW: A Low-Cost Technique to Reduce NBTI-Dependent Parametric Failures in L1 Caches
      Shrikanth Ganapathy (EPFL - Ecole Polytechnique Federale de Lausanne), Ramon Canal (UPC), Antonio Gonzalez (Intel and UPC) and Antonio Rubio (UPC)
    • Multi-Accelerator System Development With The ShrinkFit Acceleration Framework
      Michael Lyons, Gu-Yeon Wei and David Brooks (Harvard Univ)
    • Ternary Cache: Three-valued MLC STT-RAM Caches
      Seokin Hong, Jongmin Lee and Soontae Kim (KAIST)
    • Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture
      Jaehyeong Sim, Jun-Seok Park, Seungwook Paek and Lee-Sup Kim (KAIST)
    • Accurate Prediction of Detailed Routing Congestion using Supervised Data Learning
      Zhongdong Qi, Yici Cai and Qiang Zhou (Tsinghua Univ)

10/20 (Mon) 15:20 – 17:00
PA-1: Caches/Mapping
Session Chair: Jae-sun Seo (Arizona State Univ, USA)

    • SFFMap: Set-First Fill Mapping for an Energy Efficient Pipelined Data Cache
      Pritam Majumder, Venkata Kalyan T and Madhu Mutyam (IIT, Madras)
    • ReMAP: Reuse and Memory Access Cost Aware Eviction Policy for Last Level Cache Management
      Akhil Arunkumar and Carole-Jean Wu (Arizona State Univ)
    • Dynamic Associative Caches: Reducing Dynamic Energy of First Level Caches
      Karthikeyan Dayalan, Meltem Ozsoy and Dmitry Ponomarev (Binghamton Univ)
    • Increasing Cache Capacity via Critical-words-Only Cache
      Cheng-Chieh Huang and Vijay Nagarajan (Univ of Edinburgh)
    • Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration
      Jianxing Wang, Pooja Roy, Weng-Fai Wong (National Univ of Singapore), Xiuyuan Bi and Hai Li (Univ of Pittsburgh)

Special Session A: The Semiconductor Roadmap 2.0
Session Chair: Jung-Hoon Chun (Sungkyungkwan University, Korea)

    • ITRS 2.0: Toward a Re-Framing of the Semiconductor Technology Roadmap
      Juan-Antonio Carballo (Broadcom), Wei-Ting Jonas Chan (UCSD), Paolo A. Gargini (Stanford), Andrew B. Kahng (UCSD) and Siddhartha Nath (UCSD)
    • More Moore Landscape for System Readiness - ITRS2.0 Requirements
      Mustafa Badaroglu (Qualcomm)
    • The ITRS MPU and SOC System Drivers: Calibration and Implications for Design-Based Equivalent Scaling in the Roadmap
      Wei-Ting Chan, Siddhartha Nath and Andrew B. Kahng (UC San Diego)
    • Updates of the ITRS Design Power and Cost Models
      Gary Smith (Gary Smith EDA)

10/20 (Mon) 17:00 – 18:40
TVS: Reliability, Security, Test and Verification
Session Chair: Chengmo Yang (Univ of Delaware, USA)

    • A lightweight and open-source framework for the lifetime estimation of multicore systems
      Cristiana Bolchini, Matteo Carminati, Marco Gribaudo and Antonio Miele (Politecnico di Milano)
    • Advanced Modes in AES: Are they Safe from Power Analysis based Side Channel Attacks?
      Darshana Jayassinghe (UNSW), Roshan Ragel (UOP), Angelo Ambrose, Aleksandar Ignjatovic and Sri Parameswaran (UNSW)
    • Built-In Self-Test for Interposer-Based 2.5D ICs
      Ran Wang, Krishnendu Chakrabarty (Duke Univ) and Sudipta Bhawmik (Qualcomm)
    • SOS3: Three-Step Optimization of Pre-Bond TSV Test for 3D Stacked ICs
      Bei Zhang and Vishwani Agrawal (Auburn Univ)
    • Equivalence Verification For NULL Convention Logic (NCL) Circuits
      Vidura Wijayasekara, Sudarshan Srinivasan and Scott Smith (North Dakota State Univ)

Embedded Tutorial: Advanced Interconnect Design: ECO and 3D Integration
Organizers: Ibrahim Elfadel (Masdar Institute of Science and Technology, UAE), Hui-Ru Jiang (National Chiao Tung Univ, Taiwan)

    • Metal-only Engineering Change Order Optimisation
      Hui-Ru Jiang
    • TSV physical design for 3D IC
      Ibrahim Elfadel



10/21 (Tue) 10:20 – 12:00
CSA-2: Non-volatile Memory
Session Chair: Koji Inoue (Kyushu Univ, Japan)

    • Exploit Asymmetric Error Rates of Cell States to Improve the Performance of Flash Memory Storage Systems
      Congming Gao, Liang Shi, Kaijie Wu (Chongqing Univ), Chun Jason Xue (City Univ of Hong Kong) and Edwin H-M. Sha (Chongqing Univ)
    • Write-aware Random Page Initialization for Non-Volatile Memory Systems
      Fei Xia, Dejun Jiang, Jin Xiong and Ninghui Sun (Institute of Computing Technology, Chinese Academy of Sciences)
    • Loose-Ordering Consistency for Persistent Memory
      Youyou Lu, Jiwu Shu, Long Sun (Tsinghua Univ) and Onur Mutlu (Carnegie Mellon Univ)
    • (Invited) Design Space Exploration of an NVM-based Memory Hierarchy
      Seungjae Baek, Daeyeon Son, Dongwoo Kang, Jongmoo Choi (Dankook Univ, Korea), and Sangyeun Cho (Samsung, Korea)

EDA-1: Physical Design

Session Chair: Hui-Ru Jiang (National Chiao Tung Univ, Taiwan)

    • Timing Characterization of Clock Buffers for Clock Tree Synthesis
      Can Sitik, Scott Lerner and Baris Taskin (Drexel Univ)
    • Improving Power Delivery Network Design by Practical Methodologies
      Chia-Chi Huang (National Chiao Tung Univ), Chang-Tzu Lin (Industrial Technology Research Institute), Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, (National Chiao Tung Univ), Chia-Hsin Lee and Ding-Ming Kwai (Industrial Technology Research Institute)
    • Chip Clustering with Mutual Information on Multiple Clock Tests and its Application to Yield Tuning
      Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu and Jing-Jia Liou (National Tsing Hua Univ)
    • Simultaneous EUV flare- and CMP-Aware Placement
      Chi-Yuan Liu and Yao-Wen Chang (National Taiwan Univ)
    • Modeling and Analysis of Phase Change Materials for Efficient Thermal Management
      Fulya Kaplan, Charlie De Vivero, Samuel Howes (Boston Univ), Manish Arora (AMD), Houman Homayoun (George Mason Univ), Wayne Burleson (AMD), Dean Tullsen (Univ of California, San Diego) and Ayse Coskun (Boston Univ)


10/21 (Tue) 13:20 – 15:00
PA-2: Dynamic Optimization Techniques for Power, Performance
Session Chair: Sunil Khatri (Texas A&M Univ, USA)

    • Improving Multilevel PCM Reliability through Age-aware Reading and Writing Strategies
      Chen Liu and Chengmo Yang (Univ of Delaware)
    • BarTLB: Barren Page Resistant TLB for Managed Runtime Languages
      Xin Tong and Andreas Moshovos (Univ of Toronto)
    • A Thread-aware Adaptive Data Prefetcher
      Jiyang Yu and Peng Liu (Zhejiang Univ)
    • Dynamic Front-End Sharing In Graphics Processing Units
      Tao Zhang and Xiaoyao Liang (Shanghai Jiao Tong Univ)
    • Leveraging Dynamic Slicing to Enhance Indirect Branch Prediction
      Walid Ghandour and Nadine Ghandour (Lebanese Univ)

Special Session B: Variability, Modeling and Margin at 10nm
Session Chair: Kwangok Jeong (Samsung, Korea)

    • DFM is Dead – Long Live DFM
      Dave Pietromonaco, Brian Cline, and Rob Aitken (ARM)
    • The End of Layout Freedom: Implications of Process, Rules, Manufacturability and Models at 10nm and Beyond
      Swamy Muddu (Qualcomm)
    • Pattern-Restricted Design at 10nm and Beyond
      Rani S. Ghaida (GLOBALFOUNDRIES), Yasmine Badr (UCLA), and Puneet Gupta (UCLA)
    • Improved Signoff Methodology with Tightened BEOL Corners
      Tuck Boon Chan (Qualcomm), Sorin Dobre (Qualcomm), and Andrew B. Kahng (UCSD)

10/21 (Tue) 15:20 – 17:00
CSA-3: Hardware-software Interaction
Session Chair: Madhu Mutyam (IIT Madras, India)

    • Accelerating Divergent Applications on SIMD Architectures Using Neural Networks
      Beayna Grigorian and Glenn Reinman (Univ of California, Los Angeles)
    • Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems
      Satoshi Imamura (Kyushu Univ), Hiroshi Sasaki (Columbia Univ), Koji Inoue (Kyushu Univ) and Dimitrios S. Nikolopoulos (Queens Univ Belfast)
    • QoS Management on Heterogeneous Architecture for Parallel Applications
      Ying Zhang (Louisiana State Univ), Li Zhao, Ramesh Illikkal, Ravi Iyer, Andrew Herdrich (Intel) and Lu Peng (Louisiana State Univ)
    • Software Pipelining of Dataflow Programs with Dynamic Constructs on Multi-Core Processor
      Yogesh Murarka, Pankaj Gode, Sirish Kumar Pasupuleti and Soma Kohli (SRI-B India)
    • Intra-task Scheduling for Storage-less and Converter-less Solar-Powered Nonvolatile Sensor Nodes
      Daming Zhang, Li Shuangchen, Ang Li, Yongpan Liu, Huazhong Yang (Tsinghua Univ) and Sharon Hu (Univ of Notre Dame)

LCD-2: Emerging Circuits and Computing Concepts
Session Chair: Ramon Canal (Universitat Politecnica de Catalunya, Spain)

    • Boolean Circuit Design using Emerging Tunneling Devices
      Behnam Sedighi, Joseph J. Nahas, Michael Niemier and X. Sharon Hu (Univ of Notre Dame)
    • Compact and Accurate Stochastic Circuits with Shared Random Number Sources
      Hideyuki Ichihara, Daiki Sunamori, Shota Ishii, Tsuyoshi Iwagaki and Tomoo Inoue (Hiroshima City Univ)
    • Analyzing and Controlling Accuracy in Stochastic Circuits
      Te-Hsuan Chen and John P. Hayes (Univ of Michigan)
    • Low Write-Energy STT-MRAMs using FinFET-based Access Transistors
      Alireza Shafaei Bejestan, Yanzhi Wang and Massoud Pedram (Univ of Southern California)
    • Variation-Aware Joint Optimization of Supply Voltage and Sleep Transistor Size for 10nm FinFET Technology
      Qing Xie, Yanzhi Wang, Shuang Chen and Massoud Pedram (Univ of Southern California)

10/21 (Tue) 17:00 – 18:30
Poster Session (see list of posters below)



10/22 (Wed) 8:30 – 10:10
PA-3: Architecture and Design
Session Chair: Peng Liu (Zhejiang Univ, China)

    • The Heterogeneous Block Architecture
      Chris Fallin  (Carnegie Mellon Univ), Chris Wilkerson (Intel) and Onur Mutlu (Carnegie Mellon Univ)
    • An Asynchronous Network-on-Chip Router with Low Standby Power
      Amr Elshennawy and Sunil Khatri (Texas A&M Univ)
    • NVSleep: Using Non-volatile Memory to Enable Fast Sleep/Wakeup of Idle Cores
      Xiang Pan and Radu Teodorescu (The Ohio State Univ)
    • Design-Effort Alloy: Boosting a Highly Tuned Primary Core with Untuned Alternate Cores
      Elliott Forbes (North Carolina State Univ), Niket Choudhary (Qualcomm), Brandon Dwiel (North Carolina State Univ) and Eric Rotenberg (Qualcomm)
    • Energy Efficiency Improvement of Renamed Trace Cache through Reduction of Dependent Path Length
      Ryota Shioya and Hideki Ando (Nagoya Univ)

10/22 (Wed) 10:30 – 12:10
CSA-4: Architectural Framework
Session Chair: Jang Woo Kim (POSTECH, Korea)

    • Hermes: Architecting a Top-Performing Fault-Tolerant Routing Algorithm for Networks-on-Chips
      Costas Iordanou, Vassos Soteriou (Cyprus Univ of Technology), and Konstantinos Aisopos (Microsoft)
    • An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators
      Yaman Umuroglu and Magnus Jahre (Norwegian Univ of Science and Technology)
    • Fair Share: Allocation of GPU Resources for Both Performance and Fairness
      Paula Aguilera, Nam Sung Kim and Katherine Morrow (Univ of Wisconsin-Madison)
    • Dynamic Variability Management in Mobile Multicore Processors under Lifetime Constraints
      Pietro Mercati, Francesco Paterna (UCSD), Andrea Bartolini (ETH Zurich), Luca Benini (Univ. Bologna) and Tajana Simunic Rosing (UCSD)

EDA-2: System-Level Design and Power Management
Session Chair: Jae Wook Lee (LG Electronics, Korea)

    • Design Space Exploration of Multiple Loops on FPGAs using High Level Synthesis
      Guanwen Zhong, Vanchinathan Venkataramani (National Univ of Singapore), Yun Liang (Peking Univ), Tulika Mitra (National Univ of Singapore) and Smail Niar (Univ of Valenciennes and Hainaut-Cambresis)
    • Storage-allocation to Sequential Structures in High-Level Synthesis assisted Prototyping
      Vinay B. Y. Kumar, Shovan Maity and Sachin Patkar (IIT Bombay)
    • HW/SW Partitioning for Region-based Dynamic Partial Reconfigurable FPGAs
      Yuchun Ma (Tsinghua Univ), Jinglan Liu (Beijing Univ of Posts and Telecommunication), Chao Zhang (Tsinghua Univ) and Wayne Luk (Imperial College)
    • Power Supply and Consumption Co-Optimization of Portable Embedded Systems with Hybrid Power Supply
      Xue Lin, Yanzhi Wang (Univ of Southern California), Naehyuck Chang (Seoul National Univ) and Massoud Pedram (Univ of Southern California)
    • Automated Generation of Battery Aging Models from Datasheets
      Massimo Petricca (Politecnico di Torino), Donghwa Shin (Yeungnam Univ), Alberto Bocca, Alberto Macii, Enrico Macii and Massimo Poncino (Politecnico di Torino)


    • Optimal Variable Ordering in ZBDD-based Path Representations for Directed Acyclic Graphs
      Stelios Neophytou (Univ of Nicosia) and Maria Michael (Univ of Cyprus)
    • Hybrid Modeling Attacks on Current-based PUFs
      Raghavan Kumar and Wayne Burleson (Univ of Massachusetts at Amherst)
    • CoolBudget: Data Center Power Budgeting with Workload and Cooling Asymmetry Awareness
      Ozan Tuncer (Boston Univ), Kalyan Vaidyanathan, Kenny Gross (Oracle) and Ayse K Coskun (Boston Univ)
    • Refresh Enabled Video Analytics: Implications on Power and Performance of DRAM Supported Embedded Visual Systems
      Siddharth Advani, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin Irick (Pennsylvania State Univ), Yong Cheol Peter Cho (ETRI, Korea), Jack Sampson and Vijaykrishnan Narayanan (Pennsylvania State Univ)
    • Exploiting Natural Redundancy in Visual Information
      Chris Lee, Kevin Irick, Jack Sampson (Pennsylvania State Univ), Chuanjun Zhang (Intel) and Vijaykrishnan Narayanan (Pennsylvania State Univ)
    • Dark Silicon and Congestion Aware Power Management for Manycore Systems under Dynamic Workloads
      Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani (Univ of Turku), Awet Yemane Weldezion (Royal Institute of Technology), Pasi Liljeberg, Juha Plosila (Univ of Turku), Axel Jantsch (Royal Institute of Technology) and Hannu Tenhunen (Univ of Turku)
    • Cache Design for Mixed Critical Real-Time Systems
      N G Chetan Kumar, Sudhanshu Vyas (Iowa State Univ), Ron K. Cytron, Christopher D. Gill (Washington Univ in St. Louis), Joseph Zambreno and Phillip H. Jones (Iowa State Univ)
    • Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces
      Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead (Drexel Univ)
    • ScalaHDL: Express and Test Hardware Designs in a Scala DSL
      Yao Li (Shanghai Jiao Tong Univ), Antonio Roldao Lopes, Zhouyun Xu, Zhengwei Qi (Morgan Stanley) and Haibing Guan (Shanghai Jiao Tong Univ)
    • PRATHAM: A Power Delivery-Aware and Thermal-Aware Mapping Framework for Parallel Embedded Applications on 3D MPSoCs
      Nishit Kapadia and Sudeep Pasricha (Colorado State Univ)